Electromagnetic Crosstalk Considerations In Low Power Designs

A method for shrinking the size and power of designs, with less margin and fewer decaps.

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By Magdy Abadir, Padelis Papadopoulos, and Yehea Ismail


Power consumption continues to be a critical design metric in high-performance mobile electronics. In order to meet the aggressive power budget targets, chips today need to operate at extremely low power levels, which increases the critical signals’ susceptibility to electromagnetic (EM) crosstalk effects.

Because a low-power SoC has much smaller noise margin, small amounts of switching activities that cause ringing on the power delivery network (PDN) can adversely affect the chip’s performance.

In today’s leading-edge design, clock and power distribution networks are the main contributors of an integrated circuits failure mechanism, such as jitter, clock skews, electromigration, coupling noise and power distribution droops. Hence, both performance and risk aversion are dependent on the robustness of clock and power distribution network design, making accurate modeling of inductive and magnetic effects a fundamental requirement.

For example, consider a power distribution network that is feeding a digital block with high current demand and very fast switching activity (i.e., drawing high amounts of current in very fast transients). Such an activity would result in ringing on the power distribution network (PDN) that is proportional to the inductance (L) and the rate of switching activity (di/dt). As switching activity increases, the magnitude of the ringing will increase, as well as the noise level on critical and/or sensitive high frequency signals through coupling with PDN.

Power consists of dynamic power and leakage current. Dynamic power is dependent on total load capacitance, supply voltage and operating frequency. Lowering any of these parameters can result in lower dynamic power. But a common design methodology for PDN is to insert enough decaps to filter the spikes on the network due to simultaneous switching noise that can result in large current spikes at the clock edges. Leakage power is caused by the current path between supply and ground when NMOS and PMOS channels of a CMOS gate are simultaneously turned on during the rise and fall time of the input signal.

It is possible to model PDN and determine the size and location of decap placement solely on RC time constant. However, LC time constant dominates the RC time constant in most PDN designs, so ignoring inductive effect can result in significant overdesign. Including LC time constant will result in smaller size and fewer number of decaps, which in turn will significantly reduce the total decap and total dynamic power consumption, as well as leakage current.

Meeting the low power demands of today’s chips require accurate and complete model of inductance and electromagnetic interconnect and comprehensive understand of electromagnetic crosstalk impact on PDN need to be part of the physical design process, from early in the design cycle to sign-off.

Padelis Papadapoulos is the engineering director at Helic. Yehea Ismail is a professor in the Department of Electronics and Communications Engineering at The American University in Cairo, Egypt.



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