Examining Mechanical Deformation In Advanced Logic Devices To Enhance Yield

By Sandy Wen and Jacky Huang

As dimensions shrink and aspect ratios increase in advanced logic devices, it is increasingly important to reduce structural device variation. Structural device variations can be a proxy for device yield. These variations might include critical dimension (CD), gate CD, gate height, and proximity between neighboring vias.

One contributor to structural device variation is mechanical deformation, which may be caused by intrinsic material stress and thermal expansion. Virtual fabrication can help track the evolution of stress deformation during device manufacturing to understand and mitigate the effects of deformation in logic processing.

The Semiverse Solutions team studied stress-related deformation in an advanced FinFET process flow that was modeled using the SEMulator3D virtual fabrication platform. Stress-related deformation was tracked during polysilicon sacrificial gate creation and removal to evaluate whether these deformations would lead to process module failures.

With SEMulator3D, engineers can conduct virtual experiments on FinFET SRAM (depicted here) and other semiconductor devices.

Stress evolution

During FinFET gate formation, polysilicon is etched to form a sacrificial gate structure. After source/drain formation, the region surrounding the gate is filled with dielectric material. The polysilicon structure is then removed to create a trench that is filled with gate dielectric and work function metals.

The gate dimension is impacted by stress deformation throughout wafer processing. When polysilicon intrinsic stress is varied, the gate will expand or shrink during the etch process due to compressive or tensile stress, resulting in variations in CD and gate height (Figure 1).

Fig. 1: Gate structural variation due to intrinsically stressed polysilicon. (Top) Gate critical dimension. (Bottom) Gate height. 

Later in the process flow, additional deformation occurs in the gate region, due to intrinsically stressed dielectric films and stress in the source/drain region located between gates.

Deformation-induced gate CD shrinkage during the nominal sacrificial gate removal process can leave behind polysilicon residue in the trench end (Figure 2).

Fig. 2: When the polysilicon gate material becomes more tensile, the nominal sacrificial gate removal process can no longer entirely remove the gate material, leaving residue in the trench end. 

Virtual experiments

To understand the effects of stress deformation on gate removal, two sets of virtual experiments were conducted to evaluate the process window for gate-etch and removal processes:

• One without any mechanical stress awareness
• One tracking the evolution of stress deformation during processing

For each experiment set, parameters across several process modules were varied to optimize the process window and achieve a prespecified gate CD, while ensuring that no polysilicon remained after the gate removal step.

Study results

There was a significant difference between “In Spec %” (the success rate of achieving specified measurement ranges across all processes) for both sets of experiments. Without stress awareness, the In Spec percentage exceeded 50% over a wide process window (Figure 3).

In contrast, more potential failures were identified when the impact of mechanical stress was included in the process model. When the evolution of stress deformation was included in the simulation, the In Spec percentage decreased to less than 45%.

Thus, we concluded that the optimal process window for this set of processes cannot be achieved without accounting for mechanical stress.

Fig. 3: For the gate CD process window: (Left) Without mechanical stress awareness, the In Spec% (red line) exceeds 50%, even at larger process windows (window size). (Right) In contrast, with stress deformation evolution, the In Spec% did not exceed 45%. 

By using stress-aware virtual experiments, we have the potential to gain a greater understanding of the impact of mechanical stress on structural device deformation and variation and how to set process windows to improve yield.

Optimizing material intrinsic stresses and implementing device structure changes can also be explored with stress-aware virtual fabrication to limit stress-induced yield loss during semiconductor manufacturing.

Jacky Huang is a software engineer at Semiverse Solutions R&D Taiwan, Lam Research.