Executive Insight: Taher Madraswala

Open-Silicon’s president sounds off about the challenges of continued innovation, new business models, and why there is renewed interest at established process nodes.


Semiconductor Engineering sat down with Taher Madraswala, president of Open-Silicon, to talk about future challenges, opportunities and changes. What follows are excerpts of that interview.

SE: What worries you most?

Madraswala: What worries me at the industry-level is the growing effect that business constraints are having on product innovation. We’ve done a very good job of advancing the manufacturing technology – like shrinking from 20nm to 16nm and 14nm. We have proven it to ourselves that we can solve very difficult technical problems. But it’s the business side that needs to change. Collectively, the industry needs to find a way to bring innovation back to the levels we used to have in the early 2000s. For example, we have not moved design starts from 28nm to 16nm as fast as we wanted to purely because of the growing cost of designs. As we create more complex architectures, we must find ways to enable the industry to foot that bill in order to continue to encourage innovation. If we don’t, we’re going to shrink the market to the point where we will not be able to try new things. If a 16nm design is going to cost $40 million to $50 million, how many companies can afford to take the risk of innovation? The business angle has become a key barrier. People are thinking that instead of spending $50M for a 16nm design, maybe they can spend $1.5 million at 130nm to try a new idea and see if it works.

SE: Define innovation. Is it innovation in business, in packaging or in trying to squeeze more onto a piece of silicon?

Madraswala: It’s innovation in design and trying out new things for consumers. It’s trying out a new protocol or a new algorithm to explore the benefits of sensor-based applications. It’s about technical innovation. What worries me is that new business constraints can impact decisions that allow companies to take the risks like they used to. As the cost of doing business is going to go up, many companies will not be able to pursue technical innovation that they used to do.

SE: What type of solutions do you see? Can innovation come out of stacking dies and new architectures as opposed to just going to 16/14nm and then 10nm and 7nm?

Madraswala: For sure, the writing is on the wall that it will be more expensive to do system-level solutions in the future because of rising mask costs, EDA tools, chip complexity and software development. This means the overall cost of the platform is going to increase. While the cost of design is increasing, there is an opportunity to reduce that — and lower risk — by selecting partners with the right expertise. Such a partner can often do design work faster and with lower costs, reduce the risk of multiple tapeouts and manage the supply chain to optimize part costs. The overall cost can be reduced just by doing fewer tapeouts. You can then lower the cost through aggregation and improving upon repeated design steps—that can reduce the cost by 30% to 40%, which directly impacts the business model. We have created centers of excellence, staffed with people who know how to do these things best, to help our customers improve time-to-market, reduce risk and lower design costs.

Another potential solution can be to use 2.5D and 3D stacking, which creates ways to mix and match chip-components rather than spend lots of money on a monolithic 14nm die with low yields and high mask costs. This approach allows products to be divided up into multiple die. As a result, some functions can be at a less expensive node, mixed with other functions that require high frequency or new low power techniques. So you can use 2.5D and 3D as a vehicle to put together a customized, system solution with lower cost of development. That is one way to enable innovation.

SE: Is the value you bring to the table based on doing more chips, or is it knowledge of one IP block works better than another and what works together?

Madraswala: The value we bring is a consequence of us doing similar designs over and over again – lots of experience. There are efficiencies we can provide by improving the same steps of design. For example, we’ve created Technology Center of Excellence around ARM core hardening. We can automate a lot of ASIC design steps so we can leverage our compute farms to improve throughput times and speed up the design closure. Faster design time means lower cost. We also can add value by proactively guiding customers to what IP works best for them, where to take a risk and where not to take a risk. Which IP has gone into high-volume production and which ones have not? What protocols work best? Today, a lot of customers come to us to hand over designs at the spec level. A lot of the innovation happens during the early phase of architecture definition. Having seen lots of silicon, we are in the best position to guide a customer on how to translate their ideas into high performance architectures that will ultimately yield for profit. We’ve done over 200 different SoCs in the networking, telecom, storage, computing and multimedia areas. We have a huge vault of best-known methods that our customers can leverage to create differentiation in power, performance and area for their ASICs.

SE: So is the big challenge today technology or business?

Madraswala: It’s more business and some technology. We saw a big change in design starts when we moved from 65nm to 45nm. A large number of players dropped out of the market. Even today we have customers who have stayed at 65nm because they cannot make a business case for moving from 65nm to 40nm. The volume they ship does not justify them to move.

SE: But there’s a lot of innovation at those nodes, too, right?

Madraswala: That’s correct. And the price of making chips at those nodes has now come down enough that more businesses can generate positive earnings at those nodes. What they shelved four years ago, when a 40nm mask was $2 million, has now become viable with mask costs becoming affordable. And where the cost of the design used to be $11 million, today it’s less than $5 million. That’s why the business side is changing the industry.

SE: There seems to be more interest in new architectural approaches, as well—ideas such as near-threshold computing, FD-SOI at 28nm, and stacked die. So is the innovation flowing backward from the front end?

Madraswala: It comes down to who is able to afford 16nm and what will drive them to spend that kind of money. There are very few businesses that can drive the market to a system solution that includes the software, the channel to sell and to support it. We are seeing the industry experimenting everywhere again, and we will drive some of that.

SE: So aside from the biggest chipmakers, where else will the innovation come from?

Madraswala: There are enough smart kids graduating every year where they will want to try something that can change the world. They just need an avenue to transform their ideas into real platforms. Some of them will probably get about $8 million to $10 million in funding and companies like us will help them achieve their dream.

SE: How do stacked die fit into this?

Madraswala: We’re going to break big problems into smaller problems and solve the small problems independently to stack them up on a 2.5D plane with an interposer. The end user doesn’t care how we solve the problem as long as it works at a price point they can afford. This approach also helps reduce time-to-market, design costs and risk.

SE: What pieces are missing to make it all work?

Madraswala: As a company, I would like to have my hands around some frequently used IP. Today we rely on Synopsys, ARM and Cadence to provide this to us. To give our customers a jump-start on development, we also develop some of our own IPs, like memory controllers for high-bandwidth low latency solutions. And we have created IP in the form of pre-verified logic modules to speed ASIC development times and reduce risk. Some of our customers, like the graphics and vision processing guys, need niche interfaces to connect to the large memory buffers they use to manipulate the data. We can use all these to put together a superior solution for them. That’s an area where we are investing.

SE: Will that be acquisition or internal growth?

Madraswala: For now we’re doing it organically. We’ll continue to hire engineers and grow internally, but at some point an acquisition may make sense.

SE: There has been a noticeable lack of new blood coming into the hardware industry in the United States and Europe. Will there be enough young people coming in from places like China and India to supply new engineers?

Madraswala: The center of the universe for semiconductors is still Silicon Valley. From an age group perspective, I still see that there are young people joining the industry. Although there are not as many as there used to be. It’s not a problem for now, as the veterans aren’t retiring right now. We’ll make sure that there is enough reward associated with our industry to attract the younger generation to take over this industry before most of us age and bow out.

SE: With software coming into the design process, will that help provide that infusion?

Madraswala: We’re seeing the same thing. At 130nm and 90nm, there was a focus on more functions being put into ASICs, which required more processing power with certain heat dissipation. Today, if you’re doing an ASIC for the multimedia industry, an image is captured on a camera that’s part of the system. It’s so miniaturized that it captures the light, transmits the image, goes into a system that works on the digitized data and displays it. If you want to do it all in the same package, the software plays an integral part. It’s the glue. To verify that system will work you have to run the software before it ships to make sure it works together. That might even be a 2.5D or 3D solution. These all used to be separate chips. Now you have to run software tests to make sure it all works in one module.

SE: Where does the Internet of Things fit into your world?

Madraswala: It’s certainly the industry buzzword. The industry is looking for the killer app that will connect all the devices. Cisco says there will be 50 billion connected devices by 2020. There will be billions of dollars of revenue coming out of it. My view is that it’s a good concept, but we still need to see commercially viable apps to glue it all together. We are also still struggling to define the security protocol for communicating from one device to another device. We’re trying to answer whether the device in the automobile and the one in the plane and the one on the human body will be able to talk to each other safely and securely. Today all these devices are evolving separately on their own. Laws that govern the building and deployment of medical devices are much different from those that govern the airline industry. It will take a while to bring this to work all together.

SE: Are you getting demand for security?

Madraswala: We haven’t seen a lot of it yet because people are still discussing what’s needed. We are the enablers. We have started looking into it, but it’s still at the discussion level. We are participating in industry-level discussions to see what it means in terms of secure protocols. Does it need to be encrypted in a certain way, and is it common across all devices? The industry doesn’t know yet. We are working on a blueprint for how all of these devices will work together.

SE: Is there a push to consolidate players in your market?

Madraswala: Not in our space. The need for players like us will only grow. Large companies are going to add value at a much higher level. We help them do things more efficiently—faster, cheaper, better. I don’t see that consolidation will happen anytime soon. I do expect there to be other new players, though. There are four or five companies coming up in India and there are others in China. There will be room for everyone to operate in their own territories and there will be enough business for all. SoC starts will grow in double digits at least through 2019. There will be IoT and wearable design starts that will keep this engine running for a long time to come

SE: One last question—where do you see the most opportunity and growth in terms of regions?

Madraswala: The majority of our business has come from North America, with some opportunities in Europe. We’re seeing consolidation in Japan, so there is a fall in SoC starts there. China remains a hot market. India continues to be implementation-oriented. They are just starting to innovate and participate in pushing new ideas to the world, and they are beginning to take risks and venture into the unknown. Last year we saw some traction in Brazil as well, mostly for analog/mixed-signal devices.


Byungchun Yang says:

Hi Ed,

Can we say that, as IC devices are getting smaller than 22nm node level, transistor portion of IC devices gets slightly faster but with more leakage problem, while Cu interconnect portion degrades much in yield, speed (resistance), leakage and mechanical stability? In another word, we gain a little in FEOL, and loose a lot in BEOL portion of the chips as we miniaturize devices further below 22nm node. Intel has shown that they could not shrink Cu interconnects, but stayed at 28nm node size (54nm CD for M1) when they released the 22nm node Ivy Bridge chips with 22nm node transistor portion. I don’t know how they solved the problem coming from the shrunk line-to-line distance, though.

To summarize, we won’t get better performance as we go down below 22nm node design rule since via and line resistances will overshoot exponentially, via bottom cleaning is getting more and more difficult, and yield will go down in BEOL portion of IC chips. This problem is deeply rooted in current faulty BEOL process in which via bottom cleaning is done with H radical cleaning alone not allowing Ar sputter etch, and a complete cap opening is dangerously done without protecting via sidewalls. I recommend industry to try a new damascene process named embedded via damascene process as depicted in US 8,207,060. You will be able to gain a lot in yield, performance such as speed, and interconnect reliability.

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