Experts At The Table: 3D Stacking

First of three parts: The importance of through-silicon vias; the available of tools and standards; best guesses for how the technology will roll out.


By Ed Sperling
Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta. What follows are excerpts of that roundtable discussion.

SemiMD: 3D stacking means different things to different people. The type of 3D stacking talked about by companies such as IBM and Freescale is different from putting older generations of analog IP on top of new technology. What’s likely to really take off and when?
Gianfagna: The stock configurations will be first. What I’ve seen is processor on one layer, memory on another, and the sexy thing is ‘wide I/O, narrow I/O, silicon interposer.’ How do you really optimize memory and processor?
Radojcic: It is a memory and logic combination and there are two solutions. One is side by side with an interposer for guys that can tolerate a big footprint. There is wide I/O and logic. There also is the version without an interposer that some companies are pursuing. There is a consensus in the industry that all these types of technology have traction and will hit product with 3D.
Wingard: It’s important to look at why that’s so compelling. It boils down to the fact that in the last 30 years of computer architecture the processor speeds have been increasing while fundamental memory bandwidth has not. There is a chokepoint in the system where we have this large number of data requests being funneled through a single interface to external memory. Then you get onto the DRAMs themselves and they have a lot of bankable parallelism. We went to multi-bank DRAM a long time ago. What TSVs (through-silicon vias) in particular give us is a cheap way of greatly increasing the bandwidth between the logic chip and the memory. We can’t do it with bond wires. We have to do it with something where the cost of the connection becomes orders of magnitude cheaper. That’s what makes it compelling.
Radojcic: The value proposition is wide I/O. TSVs are the enabler.
Hogan: I’d back up even further. It’s always performance, power and cost or area. You get the opportunity for less latency. You don’t have a memory controller that’s chewing up a bunch of power. And you can integrate different process nodes to get the cost down. Xilinx is shipping a transposer rather than an interposer. They can drop four FPGAs onto that. It’s like a reference board on silicon.
Subramaniam: What we’ve been talking about with an interposer is 2.5D. It’s two pieces of silicon sitting on another substrate. It’s a packaging technology. There are several advantages to this. In a plastic substrate you are constrained by the design rules of plastic, which are hundreds of microns. If you go to silicon you are constrained by silicon design rules, which are tens of microns. What happens is that you are able to have significantly higher interconnect between chips, which you did not have in the past with plastic substrates. The reason you’re getting high bandwidth is because you’re about to have a 512-bit I/O instead of the standard 64-bit I/O. You can do that because you have the luxury of these smaller pitches on silicon. The second thing wide I/O does is improve power because you don’t have to have your typical DDR interface with an I/O buffer running at a higher voltage. With wide I/O you don’t need an I/O buffer, because with two pieces of silicon sitting so close to one another you can drive it with core voltage. That’s where you get the significant improvement in power.
Wingard: Actually, you don’t even have a PHY. There are no DLLs or PLLs.
Hogan: It’s a scheduler.
Subramaniam: So you can put in a baseband and an RF, or any other chips, and you can increase the speed at which these two chips can talk to one another. You can have more I/Os between the two of them and incorporate that. That’s the biggest advantage of silicon interposer technology. With 3D you’re going further. The devices will have active transistors in them and a TSV. But that will require significant changes in design methodology, CAD tools and design rules. The whole ecosystem needs to evolve significantly for that to happen.
Hogan: This is really what we used to refer to as hybrid technology. This idea has been around forever. We’re just introducing more technology with TSVs. It’s a 2.5D solution.

SemiMD: Is it really just packaging?
Radojcic: We spend a lot of time thinking about this. To call it packaging technology is misleading. You are going to use TSVs and TSS (through-silicon stacking) only if you are going to architect for it. You can’t just take two existing chips and slap them together. TSVs will cost more. The way you get the value out of it is by including it in the architecture. Wide I/O is an excellent example. You can do wide I/O only with TSS. You can’t do it with wires. It’s more than just packaging. It’s an integration technology.
Subramaniam: I agree. Things you can do in a multi-chip module today you can do with TSVs. But that doesn’t mean it’s the only thing you can do with TSVs.
Radojcic: But if you are trying to do multichip modules with TSVs you’re just creating a more expensive solution. You’re only going to do things with TSVs that you cannot do with multichip modules.

SemiMD: Are the design tools there?
White: The EDA industry, in general, is mindful that it needs to solve today’s problems at 28nm and 20nm outside of 3D ICs. At the same time, we also need to be investing in technologies to support 3D ICs. We need to balance our investments between both of those. Most of our efforts have 3D components. The Calibre division is working on solutions for 3D ICs and trying to judge the investment level versus the time when customers will need physical verification models. The EDA tools will come. They may not be out as quickly as some would want, but they will be available to the general market as they are needed. Our plan is to have physical verification tools in place this year.
Hogan: You’ve got to have that. And if you look at Sonics’ technology, the network on chip architecture gives you even more degrees of freedom to do high-level integration and go after performance. I think performance will drive everything.
Radojcic: The value proposition is either performance or power or form factor. But in terms of tools you have to step back and look at the application. If the first application is memory and logic you really don’t need many new tools. You need some standardization in terms of how you move design information from one tool to another. But you don’t need new tools because I’m designing one thing at a time. At some future date will be designing logic-to-logic integration, and then we will truly need new tools. People have been saying for 3D you will have to throw away all your tools. It’s not at all like that. I can design the kind of products people are talking about with a few tweaks. You may need new flows, but not new tools.
White: I agree with that. The approach we’re trying to take is to build upon the existing tools and extend them to deal with the interfaces in a more seamless way to deal with the memory and the logic underneath. You’re currently using scripts to try and deal with those interfaces. We want to connect up the memory physically and electrically with the logic underneath. Over time that will evolve to something more sophisticated where you have logic on logic so you have finer granularity.
Gianfagna: That is the good news. You don’t need to swap out the whole design perspective. A lot of our tools can be extended in a rather straightforward way to 3D design. It’s not trivial, but it is an extension of the existing methodology. It’s not tool retraining. But down the road as you start looking at thermal and mechanical stress, that’s different. You’re looking at placing TSVs that have nothing to do with connectivity. They have to do with heat dissipation. That’s weird, and it gets more difficult as we proceed. But you don’t have to bite it off all at once.
Radojcic: You don’t need new tools in the RTL to GDS II flow. But you do need new tools for exploring the value proposition. We can’t rely on past experience that came from 2D scaling to define a winning vision in 3D. We call that pathfinding. Somewhere at the tail end we will need methodologies and tools to manage the interaction of die for thermal. How do you incorporate that into corners or stress?
Hogan: I think the opportunity is at the architectural level. If I have a wide memory, it gives me more options in terms of implementation. And because we have more degrees of freedom, it gives us more options at the software level.
Subramaniam: You can’t trivialize the tools. You will need significant enhancements in terms of extraction and planning analysis—especially if you are going to do logic on logic. How do you figure out the partitioning, and then how do you model the interconnect between block A and block B? That whole area needs to be studied. And with TSVs in your ASIC you’re going to have islands and blockages that you will have to work around. This will need a lot of R&D.
Wingard: Another problem is how we’re going to share known good die between companies, which is something we’ve been trying to do for years and years. How do people deal with these very thin wafers? For me the big risk is in that area. The second big risk is in the architectural area. When we try to think about partitioning systems, where we have standard interfaces I’m not worried. It’s all the places where we don’t have standard interfaces. Will we have to come up with a new class of standard interfaces or will the way we partition a system across multiple FPGAs be one in which we don’t worry about the I/O because it’s just the I/O? Is that the model we’re going to use? I really don’t think so. How many people can afford to build four logic die and four mask sets instead of one? We’re going to need some standard interfaces.
Radojcic: I agree. You need the architecture first. Then you can worry about physical problems.