Experts At The Table: IC Manufacturing Challenges

Second of three parts: FinFET yields at different process nodes; controlling variance; differences between finFETs at 14nm and 10nm; SOI vs. bulk CMOS.


By Mark LaPedus
Semiconductor Manufacturing & Design sat down with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are excerpts of that conversation.

SMD: Intel entered the finFET era at the 22nm node and is in production now. The foundries plan to do finFETs at 14nm. What are the challenges facing the foundries in finFETs?
Hebb: The company that has already succeeded in introducing finFETs tends to introduce things a couple of generations before anyone else. But for finFETs, it’s turning out to be quite a challenge for the foundries. The foundries will get there with enough work. The foundries will get to the point relatively soon, if they are not there already, where they have working transistors. But getting it into manufacturing with yield is a little bit unpredictable. The question is how fast will they be able to come up the yield curve? The yield curve between 28nm, 20nm and then 14nm could look drastically different. Everyone will get a finFET transistor working, but who is really going to make it yield and make it manufacturable? For the foundries, another major challenge is going to make finFETs in a cost-effective way. If you think about an applications processor from a foundry, the cost is anywhere between $10 and $30. If you’re selling a high-end microprocessor for a few hundred dollars, then you can do a lot of things in manufacturing you couldn’t in a foundry.
Dixit: FinFETs are the next step to scale a device. The benefits in terms of performance and power are all very obvious for finFETs. But I don’t know how easy it is to translate planar into finFETS at the foundry level. People are talking about how to control the variance of the fin itself. I don’t think it’s that easy to take planar and fit a fin on it. Trying to do multiple design types and doing it in a timely and cost-effective manner will also be challenging. And then you put the finFET into the design as part of the ecosystem. What do you do when you have all of these old standard cell libraries without having to make any changes from planar to a 3D transistor? You also have to make sure you get the right behavior models out of it. But the question is what are the demands from the systems-level ecosystem? How widely finFETs will get used is the other question?
Mazure: What’s driving this transition is the need to reduce leakage and power consumption. Intel, for one, has introduced the first finFET called Tri-Gate. Intel is a vertically integrated company. Design and manufacturing technology go hand-in-hand. You basically impose this in a bottoms-up fashion. This is the same type of approach in memories. Once you move outside this ecosystem, you have the fabless companies and the foundries. In that ecosystem, there are different design methodologies. You also have legacy IPs. Therefore, it’s not so simple. For time to market, the industry must look at how to reuse its design methodology without throwing everything out the window and developing everything from scratch. Power management also has a lot to do with design. Going forward, there is a need for finFETs. We will see the appearance of more and more fully depleted devices. But in finFETs, I also think there are bigger challenges for the foundries. Having a finFET is probably easy. You can develop ring oscillators and SRAM bits, but nobody buys that. Having an integrated process that yields is a different story. You need to do real circuits, applications processors and basebands. But let’s not forget, for many fabless companies, 28nm is going to be a long-lived node. Not everybody is going to immediately jump on the next node and move to the foundries with finFETs at 14nm.

SMD: Will the finFET architecture at 14nm look the same at 8nm? Or will you have to start from scratch at 8nm?
Hebb: You won’t start from scratch, but I think you’ll see different materials. You’ll start to see III V materials, maybe III V channels at 8nm. It’s the same way a planar transistor at 45nm is not going to be the same at 20nm. You will see new materials. You will probably see different strain engineering, as well.

SMD: Will we see the same or different lithography at those nodes?
Dixit: If you look at memory and advanced logic today, there is some level of double-patterning going on. Logic is maybe a little bit behind. Memory has been using double-patterning for a long time. For future nodes, people are now talking about triple-patterning and quadruple-patterning. Basically, this uses today’s illumination without changing to a radically different source. So, multi-patterning will be required for some critical steps. But the question is how do you partition those things?
Wimplinger: We have our eye on next-generation lithography. We have some activity in 450mm with our nanoimprint technology. But we are not really convinced nanoimprint will be the way to do patterning in manufacturing in the long run.
Mazure: The industry has a track record of pushing the limits in optical lithography. When I started my career, we were told the end of optical was one micron. We were told optical lithography could not print things smaller than that. For future nodes, I’m sure the lithography community will figure it out.

SMD: What role will SOI and bulk play in future designs?
Hebb: I think we might see a mix of solutions. Different companies have different levels of experience with SOI. Some companies have long, long histories with SOI. Some are extremely comfortable with it. Other companies have not really taken a serious look at SOI. Those companies would have a long learning curve with SOI. Those companies would likely go the bulk direction.
Dixit: It’s not going to be a one-solution-fits-all in terms of bulk or SOI. The foundries, IDMs and other players will look for solutions that are suited for their customers.
Mazure: The industry is going fully depleted. There are two ways of going fully depleted: planar and 3D. For planar, design porting is very easy. That can address huge volumes. That can address many applications. It’s very flexible, given that SOI is an evolution from 28nm bulk technology. For the brand new designs from scratch, some companies may decide to start fresh at 14nm technology with fully depleted SOI. But there are not too many companies that will need that type of technology today. Many companies are still designing in 65nm and 40nm. The question for leading-edge chipmakers is how long do they wait in 28nm before they need to swallow the pill? This, of course, is not a question for Intel. They have already made the transition to finFETs.

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