Experts At The Table: Multipatterning

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: Will the future be more patterning, or will we be looking at things completely differently such as DSA?
Liebmann: Directed self-assembly takes design restrictions to a whole new level. It could be ready for a node that goes into high-volume development in a couple of years. But it’s definitely one of these situations where we have to be completely out of options because it is so restrictive. I could see limited introduction of directed self-assembly for patterning that is naturally somewhat restrictive, such as the fins in the finFET. It’s unidirectional, fairly fixed grating. That’s a perfect application for directed self-assembly. Doing first-level metal with directed self-assembly is different. We’d have to be a lot more desperate than we are today, and we’d have to do a lot more development on the patterning end of directed self-assembly. As we continue to back up against the wall and EUV introduction continues to be delayed, it will make sense to use things like double-sidewall self-assembly for levels where today it doesn’t make sense.
Geronimi: Double patterning was the solution we’ve chosen for now because EUV doesn’t work, and it’s one that many other companies have chosen, as well. You need to get a lot of people to solve the problem.

SMD: Reading between the lines, it looks as if we may have lots of hybrid approaches going forward. Is that correct, and what does it mean for design and cost?
Aitken: The design perspective is interesting because as the nodes move on, the design rules are becoming increasingly incomprehensible. We had people at 40nm who claimed they could understand all the rules in the book. At 32 and 28nm they were starting to admit there were a few rules they couldn’t remember. And at 20nm, nobody admits to knowing all the rules. There are single rules that take up pages of the design-rule manual for one tool. So when you look at all these things, the complexity eventually gets to the point where it’s not clear how to meet them in the first place, and then even if you do meet the rules that it will still be manufacturable. We have this iteration between design people who want to design specific shapes and fab people who want to outlaw them. The design people look for loopholes and then the design people patch the rules. It’s past the point where you can check everything against the design rule manual. We need to do something different to be assured what we’re doing is the right thing. We’ve started talking to a lot more fab people than we used to, just to make sure that when we design something and we think it’s going to work, that it actually will.
Capodieci: There is a distinction between restrictive rules and prescriptive rules. The reality is that design rules are mostly restrictive. There’s a lot of inconsistency. You can be following the rules and violating the law, in general, because they point in different directions. The move toward prescriptive design rules could be done, and certainly the introduction of pattern-based verification systems like DRC class with pattern matching moves in that direction. Designers are much more ready to start physical design using a set of well-understood constructs. If you have the well-understood constructs and the rules combined, then you have nominal verification at the end. If you allow people to do whatever they want and give them lots of laws, then you end up with anarchy and chaos.
Aitken: If you use a handshake-type of structure that says here’s the way to build context, that works.
White: Won’t that just result in revolt from the design community? You’ve reduced the degrees of freedom to create a product.
Aitken: There are different levels of this. There isn’t just a monolithic design community. Different parts of the design community interact with different parts of the ecosystem. People who do place and route don’t see the messy contacting, for example. We deliberately try to prevent the router from knowing about a lot of these rules. A lot of the people interacting with the rules are the layout designers. They just follow the rules. We find that at advanced nodes, rules are so complicated that individual layout people have a lot of trouble with them. We’ve taken a two-pronged approach of educating the layout designers to use this pattern, and then we’ve added automation techniques so the layout is generated using automated tools. The tools follow rules better than people, and they can handle very large volumes of rules.
Liebmann: Getting back to hybrid solutions, it’s quite possible we will have directed self-assembly for one layer and image deposition on another. We may have all sorts of exotic things happen as we move forward. Hybrid solutions become a little scary when we design the world into TSMC-like and Intel-like. If they’re separate hybrid solutions to compete in those markets, then we may not have enough volume to compete and justify the cost. That’s a trend that becomes worrisome—the low-cost, high-performance and high-volume markets going in somewhat different directions.

SMD: Isn’t a 3D IC a hybrid solution?
Aitken: Yes, and that’s an excellent example. As the complexity of moving from one node to the next increases, the cost tends to go up. At some point, the cost of moving to the next node will be too high. I don’t think that’s going to happen all at once, either. At some point someone will say, ‘Even though stacked die is complicated and challenging, it still seems to be cheaper than doing it the other way.’ We’ll start to see some of that as time goes on.

SMD: What happens from the tools perspective as we look at hybrid solutions?
White: At 14nm, many different approaches are being considered for different layers of the design. Each one of those approaches may drive completely different verification and analysis and simulation engines. As an EDA vendor, we have to create solutions for all of those until the industry figures out which approach makes sense. We need to support all the solutions, including the one the industry ultimately chooses. We do try to build upon the infrastructure that’s already in place at the last node, so we can leverage some of the capabilities of double patterning at 20nm at 14nm.
Liebmann: That’s also an opportunity. Once we’re at a point where the only things we can really pattern reliably are gratings, then this whole distinction of logic and memory goes away. Everything is a grating. How you pattern that grating no longer really matters. There are a lot of design efficiency benefits from that. At Carnegie Mellon they’re working on a smart memory compiler. If your logic and memory are just gratings, then you can have some very intelligent synthesis engines that put the logic right next to the memory. You no longer have to separate anything. It’s the opposite of 3D integration, where you have a memory optimized manufacturing process and a logic optimized manufacturing process and then you glue things together. We’ll get there. It’s just a matter of when it becomes a cost-effective solution.
Lin: There are concurrent advances and progress in lots of areas. 3D-IC is a very good idea—the ‘More than Moore’ approach. But there are issues such as thermal and stress and warpage, so it will be incremental. It will go from interposer to TSV. There will be concurrent progress on chip-scale approaches as well as 3D IC.

SMD: Is ST looking at hybrid solutions, as well, or is it one or the other?
Geronimi: We are looking at hybrid solutions. At some point you need to do design partitioning. You need to optimize your system to for a specific market. At some node you may optimize each of the technologies.

SMD: Given the uncertainty of the cost of developing chips and being able to generate enough volume, what impact will that have?
Aitken: You’ve already seen quite a bit of that. As people move to new nodes, the number of people willing to take a bet and jump into that—at least initially—isn’t increasing. Some of the technologies we’ve talked about, such as directed self-assembly, have the potential to open things up to more people. But there’s also a challenge with some of the grating approaches Lars was talking about. When you move to a unidirectional approach you wind up losing something in terms of power or performance. And you may wind up with a situation where it costs more and you don’t actually get any benefit from moving to the next node. That’s definitely a big challenge if that happens.