Experts At The Table: Stacked Die Reality Check

Last of three parts: Standardization in bonding/debonding; rethinking costs in a stacked die; power savings and performance boosts in stacked die; different materials; likely rollout schedules for 2.5D and 3D.

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By Ed Sperling
Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of marketing for advanced packaging and nanotechnology at Ultratech. What follows are excerpts of that conversation.

SMD: In manufacturing, one of the roadblocks appears to be bonding/debonding. How much progress is being made?
Matthias: In the past there were many different technologies for the bonding and debonding—thermal, laser, chemically assisted. It’s necessary for a manufacturer to pick one solution, but no one thing has met all the requirements. If there’s one particular process flow, today you can easily do that. You can pick the processors and line them up and manufacture them. But if you want compatibility with every conceivable process flow and every conceivable bond configuration, then it becomes trickier. What is changing is a standardization of the processes of the equipment and material independence standardization. That allows foundries and OSATs to use different materials for different applications. There may be one process for memory where you want to limit the temperature exposure. There may be another for logic and another for IGBTs (insulated gate bipolar transistors), where you want to go to a very high temperature. We have standardized processes and equipment and now it’s an open platform that allows the materials community to develop standardized solutions. There is a lot of movement in this area at the moment and there will be a lot more over the next couple of years.
Patel: This is key because the same OSATs would be doing 2.5D and 3D, where the thickness will be different and sizes will be different on the individual chips. The main issue there is that by bonding and debonding we are not inserting any defects. That will be the main challenge.
Matthias: In the past it was very difficult to think about the process flow because you were locked into one specific process. As this heads toward standardization, you can pick the process that works best. Also, sometimes it doesn’t make sense to ship very fragile wafers across the world.
Patel: I agree. If we can have a bonding/debonding and subsequent manufacturing capability in the same facility, it makes a lot more sense.

SMD: From a systemic standpoint, stacking may be less expensive, even though individual pieces may be more expensive. Does the supply chain have to be reconfigured for this?
Patel: I don’t think it’s a massive change, but it does require a mindset shift. When you look at the cost you can’t look at the individual component costs. You have to look at a product cost. From system-level to product level you have to think differently. It’s very well known that Xilinx’ decision to split a die into four pieces increases the yield. We did some rough numbers and it’s cheaper. If someone asks the cost of an interposer wafer, it’s expensive. But when you consider the cost of the whole package, it’s much more viable.
Smith: Unfortunately, Xilinx is the only case we have in production. Altera’s is a test chip. The system-level discussion for the system companies is very logical. They understand how to put these things together, and what looks to us like a major change is for them an incremental step.
Ranjan: There are also power savings in this. There are things that go onto a single-chip solution that will require higher power and greater thermal management requirements. That’s all resolved in 2.5D and 3D.
Smith: There are companies that are mixing together higher power and lower power chips to come up with what is an overall lower-power device.
Ranjan: TSVs also can handle some of the heat distribution, too.
Smith: IBM was talking about heating an entire building out of the microfluidic heat exchangers. It’s interesting research.

SMD: Presumably we will have different materials involved in stacked die. Will that go together as smoothly as CMOS on CMOS?
Patel: Image sensors are an example where they do go together well, but you do have to make sure the stresses of the integration don’t affect performance. Compatibility will be a key factor in integration.
Smith: TSVs and thermal expansion have to be analyzed by the manufacturers. There is already a lot of research out there. There are whole conferences on this. It does affect what else you include in the stack and what you bond it with.

SMD: How far are we away from standards in this area?
Patel: There are standards being created. Sematech is publishing a dashboard of different standards. From my perspective we need to bring standards together across the supply chain and make it more workable. That needs to happen first. Once you have baseline standards, you can bring in more technical standards.
Smith: From an EDA point of view, standards are still premature. The IEEE test standard is going slowly, and that’s partly because there is no driver at this point. We’ll see the major companies building these stacks gain experience, and in the process of learning we’ll start to share that. Then it can become standardized.
Pateras: You attempt to use one source for your design automation, at least initially.
Smith: Even today companies mix and match tools using standard interfaces.
Pateras: Or you do them ad hoc and then merge these standards.

SMD: Are any standards emerging on the manufacturing side?
Ranjan: For us, we are moving into the TSV space quickly. We already have equipment out there for production and R&D. There is nothing that makes it prohibitive to use this equipment right now. Standards are more meaningful on the design side. On the manufacturing side, there are no barriers today.
Matthias: In terms of standardization, the big breakthrough in the last 12 months was in bonding/debonding with the material-independent concept. In terms of the actual specification of the die and bonding together, there are already de facto standards as to what kinds of bonds you can use. At the wafer level, which is a couple years out, you’re using an oxide interface. The bonding becomes a standardized step.

SMD: When will 2.5D and 3D start showing up?
Ranjan: 2.5D is still a few years away. There is some production right now, but for meaningful volume—maybe 20,000 to 50,000 wafers per month—it’s at least two years out. TSVs are a couple years beyond that. That’s what we’re using as a projection for our equipment based on what we’ve heard from our customers.
Smith: In EDA we measure tapeouts. Aside from a few IDMs, we’re still in the test-chip phase this year. But we’re expecting early production by the end of next year, if not earlier. We’ve seen some early examples from Xilinx and Altera. The graphics guys will come next. So 2.5D already is well on the way to becoming useful. For 3D, aside from a couple examples, we won’t see that until 2015.
Matthias: By the end of next year we believe all the major players will have production capacity for both 2.5D and 3D. That’s probably not 20,000 to 50,000 wafers per month, but there will be production capacity at every player that wants to take a leading role. By the end of next year there will be a supply chain for 2.5D and 3D, although probably at a lower volume and for high-end products.
Patel: For 2.5D, 2014 will be a very interesting year. By the end of 2013 the capability will be in place. Designs already are being considered and tried out. 3D mainly depends on memory standards and memory adoption. We’ll see a package-on-package and memory-on-logic configuration first. 3D memory has its own route, which is ahead of that. 3D memory on logic could be late 2014.
Pateras: From a tapeout point of view, 2.5D is happening this year. We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts. There is no real activity in logic on logic yet.