An in-depth look at an interposer-free solution for SiPs.
System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power amplifiers, MEMS and application processors. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology which is achieved by redistributing bond pads onto mold compound has proven to shrink x, y and z dimensions of the overall SiP package. eWLB in combination with Package-on-Package (PoP) further enables higher integration of functional blocks such as silicon photonics with discrete passive components, logic and integrated passive devices (IPDs).
This paper will discuss the advantages of utilizing eWLB technology to create a SiP solution. We will review the design considerations for creating a double sided redistribution layer (RDL) on the bottom eWLB package with embedded discrete components. Board level reliability results for this package architecture will be examined. We will also review higher density requirements and the corresponding challenges for very fine line and space (5/5 or 2/2 um) whereby eWLB technology negates the need for an interposer and provides the ability to be directly attached to the substrate utilizing Copper (Cu) pillar post or lead free solder.
To read more, click here.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply