FD-SOI Foundations Ready, Say Semi Execs

By Adele Hars

SOI (especially fully depleted “FD-SOI”) was a hot topic in the video and audio interviews that Debra Vogler of SST released recently.

Here are brief summaries of the most important SOI-related interviews – with top brass from Leti, Soitec, KT, EVG and Qcept –  that she made at Semicon West ’11.

(If you need a quick backgrounder on FD-SOI basics, see this explanation from the SOI Industry Consortium.)

Laurent Malier, CEO of Leti – the process technology:

• FD-SOI 20/22nm results are good – Leti got the progress they expected, and found FD-SOI comparable to FinFETs in terms of speed gain and low-power performance.
• FD-SOI is ready for 20/22nm.  It’s low-cost, turn-key, and easily manufacturable, both in terms of the technology and the wafers.
• Planar FD-SOI will scale to the 11nm with no roadblocks beyond the usual efforts required in terms of lithography and gatestack to move to the next node.
• It’s also a simpler solution in terms of the design platforms. A lot of the IP such as I/Os can easily be transferred.

Steve Longoria, SVP, global strategic business development, Soitec – the wafers:

• Soitec supplies wafers for both types of fully-depleted structures – FinFETs and planar FD-SOI.
• Soitec has a new wafer offering: Xtreme SOI, with thin buried oxide and thin top silicon for planar FD-SOI structures.
• Working with IBM & ARM, they’ve shown two variants of planar FD-SOI: one with a 30% increase in performance at the same power, and one with 40% power savings at the same performance level.
• Soitec is currently providing thousands of manufacturing samples per month of Xtreme SOI wafers, with full qualification slated for the end of the year.
• SEH will also be producing them; millions will be supplied over the next couple of years
• Wafers for FD-SOI will scale to 11nm.
• IC Knowledge study shows FD-SOI is cost competitive and superior to bulk in terms of power-performance.
• FD-SOI is much lower risk for both design & manufacturing.

Amir Azordegan, senior director of marketing for Surfscan at KLA-Tencor – the inspection systems:

• KT has a new generation in its Surfscan family of wafer defect and surface quality inspection systems: the Surfscan SP3. The unpatterned wafer inspection platform uses deep-ultraviolet (DUV) illumination and is extendible to 450mm wafers.
• It’s for substrate development and manufacturing ≤28nm devices.
• The key advances in the new platform are sensitivity and throughput.
• The new system has been shipped to leading substrate and chip manufacturers in Asia, the United States, and Europe for use in advanced development and production lines.
• Note: see KT’s article in ASN explaining the role of the Surfscan family in SOI wafer manufacturing.

Paul Lindner, executive technology director,  EV Group – wafer bonding systems:

• EV Group (EVG) released a wafer bonding system for 450mm silicon-on-insulator (SOI) wafers: the EVG850SOI/450-mm.
• It runs at production line speed and comprises a cleaning module and pre-bonding module.
• SOI wafer provider Soitec will install, test and qualify the first EVG850SOI/450-mm system at its Grenoble, France, headquarters in Fall 2011.
• Tool development was done in cooperation with the European 450mm Semiconductor Equipment and Materials Initiative.
• He expects to see 450mm pilot-lines in 2014, moving to full production in 2016.

Robert Newcomb, executive VP of operations, Qcept Technologies – advanced defect detection technologies:

• Qcept’s nonvisual defect inspection technology is used by logic, IC and substrate manufacturers.
• New nodes drive new nonvisual defect (NVD) issues.
• Note: Qcept has been working with Soitec on NVD detection in SOI wafers for going on five years.  See their first article in ASN8.  Soitec uses the Qcept ChemetriQ system for incoming quality control of bare silicon wafers and process monitoring of SOI wafers.