Tool for assessing wafer-level warpage and RDL stress in FOCoS-CL packages.
Abstract:
“The demand for high bandwidth memory (HBM) has driven the need for advanced packaging solutions, particularly those involving fan-out layers to interconnect wafers within packages. To meet the high-bandwidth requirements of the Fan-Out Chip-on-Substrate (FOCoS) technology platform, additional layers are required. However, as the number of fanout layers increases, significant challenges arise in terms of warpage and stress, both of which pose risks to manufacturing processes and reliability testing. In this study, we employed the ANSYS Mechanical simulation software to build three-dimensional numerical models based on the FOCoS platform, encompassing both package-level and wafer-level structures. These models were used to analyze the in-process warpage and structural stress under various configurations. Simulation results indicated that wafer-level warpage increases as more fan-out layers are stacked. To mitigate this issue, we explored various factors, such as altering the carrier’s coefficient of thermal expansion (CTE), adjusting its thickness, or varying the fan-out layer thickness. Additionally, our findings revealed that the stress within the re-distribution layer (RDL) also escalates with an increasing number of fan-out layers. The findings gained from this research not only enhance our understanding of the mechanical challenges in FOCoS-CL packages but also provide valuable guidelines for the design and material selection to improve package reliability and performance.”
Publication citation: C. -H. Lai, W. -J. Yin, W. -H. Lai, C. -L. Kao, C. -C. Wang and C. Hung, “Fine-Line RDL Structure Analysis of Fan-Out Chip-on-Substrate Platform,” 2024 IEEE 26th Electronics Packaging Technology Conference (EPTC), Singapore, 2024, pp. 898-902, doi: 10.1109/EPTC62800.2024.10909677.
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