A look at the physical challenges in advanced semiconductor designs and what to do about them.
The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them.
To view this white paper, click here.
 |
 |
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply