FinFET Based Designs: Power Analysis Considerations

Design teams working on mobile, computing, networking and other low power, high performance IPs and SoCs are migrating to FinFET-based technologies. However the benefits from their smaller sizes and the ability to deliver consistent performance at ultra-low sub-1V nominal supply voltage levels is outweighed by the worsening of power noise and reliability. As mentioned in an earlier blog on Power Noise and Reliability Sign-off for the Sub-20nm FinFET Era, foundry and other data indicate that the use of FinFET not only introduces additional challenges but also increases existing ones, especially with power budgeting, voltage drop, EM and overall power noise reliability sign-off.

Power analysis serves multiple goals – it ensures a robust power delivery network design across the chip, package and board so that reliable and consistent voltage is supplied across the chip for all its operating modes. It helps designers meet their stringent power budget targets by providing early power estimates that help them understand where to optimize the design by eliminating power bugs and associated power wastage. Access to early information about thermal dissipation across chips’ different operating modes help identify proper cooling solutions. Power analysis also enables designers to meet foundry specified reliability requirements for both electro-migration (EM) and electrostatic discharge (ESD). For todays’ designs that have to simultaneously satisfy low power and high performance requirements, and especially for those targeting the use of FinFETs, it is important to meet each of these goals as part of the design process.

Power analysis starts with early and accurate power estimation – this can be performed in different stages of the chips’ design flow using multiple sets of inputs. Starting from the RTL development stage ensures the biggest design impact since it can balance early predictability (meaningful power saving opportunities) with consistent results (confidence against the final gate level power).

It is challenging to deliver consistent and accurate RTL based power numbers, especially when working with FinFET based designs where the primary emphasis is on managing dynamic or switching power. To ensure consistent and predictable RTL results, it is important to accurately determine the driver loads (or wire capacitances). For clock networks in mesh or tree configurations or large buffers driving long nets, accurately predicting interconnect capacitance without the placement and routing information can be challenging. Employing techniques that leverage physical design aware RTL power analysis methodology provide the necessary closed loop infrastructure for predictable and consistent power analysis.

Irrespective of the end applications, today’s SoCs must meet and exceed their power budget requirements. Design managers are mandating a well-defined power aware design flow and understand that the biggest power reduction opportunities are available during RTL development. However, it can be very confusing when presented with hundreds of different RTL changes that can possibly drive some form of power reduction. The opportunities that come out of a predictable and consistent power analysis flow are easier to comprehend, prioritize and incorporate. A design for power methodology based on an accurate and consistent power analysis methodology becomes key for this methodology to be effective and workable.

RTL power analysis also serves another useful purpose – it helps “prune” or identify chip activities and operating modes that can result in power supply degradation caused by high switching events. It can quickly and efficiently filter a wide range of vectors compared to gate level simulations which are significantly slower, often too late and mostly unavailable. Further discussions on various ways to perform power grid sign-off will be covered in upcoming blogs.