How to identify bugs earlier when the cost of fixing them is much lower.
Bug escape costs grow considerably with each and every subsequent step in the design flow, to the point of being exorbitantly high once at the silicon level. As a result, these high costs of bug escape are driving customers to embrace formal verification for post-silicon debug and to begin using formal far earlier in the flow for their next design projects. The Cadence JasperGold Verification System’s ability to quickly identify bugs, assure the cleanliness of sub-blocks, and verify the completeness of design fixes makes it the highest value post-silicon debug tool in the team’s arsenal.
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Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream.
Explosion of data is forcing significant changes in where processing is done.
2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.
This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.
What hoops will designers have to jump through to avoid concurrency bugs?
Why managing power is becoming more difficult, more critical, and much more expensive.
Analog circuitry stopped following Moore’s Law a long time ago, but that hasn’t always helped.
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
Can mixed-signal architectures boost artificial intelligence performance using less power?
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.
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