How to identify bugs earlier when the cost of fixing them is much lower.
Bug escape costs grow considerably with each and every subsequent step in the design flow, to the point of being exorbitantly high once at the silicon level. As a result, these high costs of bug escape are driving customers to embrace formal verification for post-silicon debug and to begin using formal far earlier in the flow for their next design projects. The Cadence JasperGold Verification System’s ability to quickly identify bugs, assure the cleanliness of sub-blocks, and verify the completeness of design fixes makes it the highest value post-silicon debug tool in the team’s arsenal.
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Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.
No shortage of alternatives as materials, packaging and architectural options grow, and plenty of startups are jumping in.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
Using the Von Neumann architecture for artificial intelligence applications is inefficient. What will replace it?
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.
Stacking die is garnering more attention, but design flows aren’t fully ready to support it.
Understanding aging factors within a design can help reduce the likelihood of product failures.
How Arm sees its role in emerging segments of tomorrow’s compute challenges.
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