Formal Verification For Post-Silicon Debug

Chipmakers wrestle with EOS, ESD and other power-related issues as leading-edge chips are incorporated into industrial and automotive applications.

Device degradation becomes limiting factor in IC scaling, and a significant challenge in advanced SoCs.

Focus is on cutting costs across the board, and it turns out there is still quite a bit to cut.

How cost-sensitive are IoT edge devices, what are the real drivers for this industry, and what is the impact on EDA and IP?

Part 2: For the IP industry to remain healthy it has to constantly innovate, but it’s getting harder.

Just relying on faster processor clock speeds isn’t sufficient for vision processing, and the idea is spreading to other markets.

The answer appears to be a resounding no, but innovation isn’t necessarily happening in the same places as in the past.

Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.