Future Directions Unknown

The semiconductor industry has been on cruise control when it comes to shrinking features, but as process technology progresses to 10nm and 7nm there will be some significant changes.

For one thing, the cost per new design will continue to rise, which means only the largest companies with the biggest market opportunity will be able to invest at the leading-edge nodes. Chips for mobile phones, as well as FPGAs and processors, will continue to press forward. Most other designs will not.

With that increasing cost also comes an increasing level of customization. Advanced designs already are a multi-way partnership between chipmakers or OEMs, foundries, EDA companies and IP companies (in some cases, EDA companies and IP companies are one and the same). Those partnerships will grow deeper at each new node as the challenges that have to be met increase and the tradeoffs continue to expand based upon use models and optimization of power, performance, area, and connectivity.

There also will be more design rules to contend with, more data to process, and more technical decisions to make about what materials to use, which architecture to utilize, including how many metal layers, and what package technology makes the most sense.

While these changes may seem obvious enough, they also raise some less obvious questions for each of the segments involved in these advanced designs. Foundries, for their part, have been built on steadily shrinking feature sizes and the rising cost of equipping advanced fabs. Processes have been developed somewhat generically to take advantage of economies of scale. One size was supposed to fit all, leading to improved performance at a lower cost (with power generally an afterthought), and limited tweaks of processes for the largest customers. In the future, the design runs will be larger, but they will be highly customized. So where will foundries invest their resources? Will they devote their energies to custom designs, or invest in platforms that can be created for a large number of customers in 2.5D or 3D configurations. These are huge investments, and no foundry is big enough to do everything for everyone.

Chipmakers, meanwhile, are uncertain about what the most cost-effective path will be for future designs that may require multi-patterning, new lithography approaches, different materials, more physical effects to deal with, and possibly a longer design cycle. Many have developed test chips at a variety of process nodes and some have even dabbled in 2.5D and 3D-IC designs. Which path they ultimately will take depends on a number of factors that are still unknown.

EDA vendors, which have enabled Moore’s Law since the 1980s, at least for the moment are relatively caught up with all the changes and are adapting their tools all the way to 7nm. But what they do beyond that isn’t entirely clear other than promising to support whoever moves in that direction. How they invest in future processes and approaches will depend on what happens over the next few years.

On the IP side, there has been talk about mass customization through programmability or more software content, but even those approaches have limits. Software is almost always behind schedule, no matter how many people are thrown at a problem. And there has been a big push to increase the number of processors and both standard and custom IP blocks on a chip.

Despite all of this effort, it’s still harder, more expensive, and more time-consuming to design, verify and fix complex SoCs—a reality that isn’t likely to change. And as foundries, chipmakers and EDA and IP vendors form tighter partnerships focused around more customized chips, predictions about likely outcomes and directions will continue to baffle even the most astute market strategists. As an industry we are entering into a period with no clear direction, and while there may be pros and cons to that, it’s certainly raising the anxiety level in a lot of places.