GDDR6: Signal Integrity Challenges For Automotive Systems

Signal integrity (SI) is at the forefront of SoC and system designers’ thinking as they plan for upcoming high-speed GDDR6 DRAM and PHY implementations for automotive and advanced driver assistance system (ADAS) applications. Rambus and its partners are closely looking at how GDDR6’s 16 gigabit per second speed at each pin affects signal integrity given the cost and system constraints for automotive designs.

At GDDR6 speeds, designers need to be concerned with three main effects in a typical channel including insertion loss, reflections, and crosstalk. There are multiple ways to mitigate these effects, including both physical and electrical design that need to be considered. In automotive designs, keeping the cost of the PCB (printed circuit board) and package low are important design criteria. The PCB should have a minimal layer count and use low-cost materials. Four to eight-layer boards are the norm for automotive PCBs. However, to support more complex applications, 12- or 16-layer PCBs are being considered. Similarly, the package should have a minimum stack-up (i.e., 4-2-4) but still allow all the necessary signals to be routed out of the SoC (system on a chip).

Insertion loss causes signals to lose strength as they go through multiple dielectric layers (metal resistance). Insertion loss is further increased due to surface roughness. To help control insertion loss, better PCB materials can be used (see below). On the electrical side, Variable Gain Amplifiers (VGA), Programmable Gain Amplifiers (PGA), and filters such as Continuous Time Linear Equalization (CTLE) inside receivers can correct this loss. The trade-off here can be made between material cost and system design complexity.

Moreover, signals can couple to adjacent signals in the package and vias on the PCB interfering with the adjacent receiver signal leading to crosstalk. These vertical paths are especially susceptible to crosstalk which can occur when signal traces are routed close to each other on the same layer or through vias. Therefore, careful design of the pin assignment (placement of signals, power and ground) is needed for GDDR6 to minimize the crosstalk effects of neighboring signals.

Vias placed under the BGA balls are also a major contributor to crosstalk effects. There are several design choices including plating through hole (PTH), blind, and buried vias.

As the name implies, PTH vias go through all the layers in one straight line and are the least expensive; the more costly are blind and buried vias. Blind vias connect an outer layer to one or more inner layers but don’t go through the entire board; and buried vias connect to any PCB layer but don’t pass to the outer layer.

For ADAS applications using GDDR6, blind and buried vias use are encouraged to improve signal integrity by minimizing crosstalk.

Also, designers need to take a close look at PCB materials to further mitigate SI effects. FR4 is the standard, however, advanced materials like Megtron 6 are being considered to maintain the lowest dielectric loss possible to minimize insertion loss. Megtron 6 is designed for high-speed systems, and its main attributes are low dielectric constant and dielectric dissipation factors, and low transmission loss, among others.

In summary, automotive system designers have their work cut out for them as they are implementing GDDR6-based SoCs. Design engineers need to evaluate the physical design options in order to optimize their system to provide the best signal integrity (i.e., performance) at the lowest price point.