Hardware Platform Based on 2D Memtransistors


A new technical paper titled “Hardware implementation of Bayesian network based on two-dimensional memtransistors” from researchers at Penn State University.

“In this work, we demonstrate hardware implementation of a BN [Bayesian networks] using a monolithic memtransistor technology based on two-dimensional (2D) semiconductors such as monolayer MoS2. First, we experimentally demonstrate a low-power and compact s-bit generator circuit that exploits cycle-to-cycle fluctuation in the post-programmed conductance state of 2D memtransistors. Next, the s-bit generators are monolithically integrated with 2D memtransistor-based logic gates to implement BNs,” states the paper.

Find the technical paper here. Published Sept 2022.

Zheng, Y., Ravichandran, H., Schranghamer, T.F. et al. Hardware implementation of Bayesian network based on two-dimensional memtransistors. Nat Commun 13, 5578 (2022). https://doi.org/10.1038/s41467-022-33053-x

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