How Long Will 28nm Last?

By Ann Steffora Mutschler
As soon as a next generation semiconductor manufacturing process node is out, bets are taken on just how long the current advanced process node will last. The 28/20nm transition is no exception.

There is certainly a benefit to moving from 40nm to 28nm. The  availability of high-k/metal gate technology offers quite a few advantages in terms of power reduction and performance improvements, particularly in the datapath and other high-speed areas.

“The high-k/metal gate process has offered design teams the ability to get reasonable (2 to 2.5GHz) speed in the datapath with good power numbers,” said Navraj Nandra, senior director of marketing for DesignWare Analog and MSIP at Synopsys. “That’s been a good addition to the process. Another factor that’s going on now is that to get low leakage power and a lower cost, TSMC and other foundries have introduced the silicon oxynitride (SiON)/polyprocess on 28nm and that is positioned as a cheaper way of getting into 28nm. It’s addressing what you could call the low end market where people are building chipsets for tablets and smartphones to offer it to a market better positioned for the price point.”

Not only is the 28nm node going strong, so is 20nm, according to Pete Hardee, low-power design solution marketing director at Cadence. Based on a survey the company took during its Low-Power Technology Summit held last month in the San Francisco Bay Area, attendees were asked which process node they were currently working on.

According to Cadence, the results were as follows:

40% — designing for 32/28nm
21% — designing for 22/20nm
16% — designing for 45/40nm
12% — designing for 65nm
11% — other

He noted that data is likely skewed for the geographic region, and is not a global number, but it shows that the 32/28nm node is definitely an extremely strong node, and that it is “relatively advanced at this life stage.” These results would seem obvious if most of these designers were in the mobile space, but interestingly, 49% of survey respondents said they were in a non-mobile market, Hardee noted.

More results from Cadence’s Low-Power Technology Summit can be found here.

Power techniques at 20nm
In terms of the power optimization and power management techniques used frequently at the 28nm node, Sudhakar Jilla, director of marketing for place and route products at Mentor Graphics, does not believe the transition from 28 to 20nm will take away any of those techniques used today. In fact, there might be a richer Vt library set from which to optimize the leakage, power optimization, etc.

But, he pointed out, that moving from bulk CMOS to fully depleted SOI provides many of the same benefits—lower voltage, lower power and equal or better performance—as moving from 28nm to 20nm bulk CMOS. “So there are different tradeoffs, and of course when it comes to power, different application segments have different power needs. But, in general, if you are going to a lower technology you can go to lower Vdd and some of these other technologies give you better power/timing tradeoffs and power/performance tradeoffs.”

Andy Inness, place and route product specialist at Mentor, noted that the power techniques at 28 and 20nm ought to be fairly similar. “You may have more options and voltages because you can go a little bit lower at 20nm. For the most part, though, it seems to be picking the right combination of node and FD-SOI and finFET, cost versus need. FD-SOI seems to have a wider range. Because you can go lower voltage at FD-SOI, it probably has a wider range of voltages to work with. So if your sleep mode is on, a wireless device can go to a lower voltage on FD-SOI than non-FD-SOI while still leaving your functional mode at the same voltage.”

That wider range gives performance versus shut down mode benefits. “You can get high performance but take advantage of the extra lower voltage for sleep mode to save the power in that because the lower voltages can give you more leakage and some other things. So being able to tolerate that lower voltage can be helpful,” he added.

The last hurrah
As design teams look to move to 20 nm, they are well aware it will be the last hurrah for planar CMOS, Hardee noted. Intel already is using Tri-Gate, its variant of finFET, at 22nm. TSMC will begin implementing finFETs at 16nm, while GlobalFoundries is adding them at 14nm.

“If you look the timescales of the planning of those nodes, there may only be about a year between 20nm being up to speed and the 16/14nm node right on its tail. This is a little quicker than the typical two years between nodes that we’ve previously seen. For that reason there may well be various considerations of whether people want to move to 20 or not.”

In addition, there’s uncertainty currently as to whether 20nm will give a performance advantage along with the promised power advantages. Leakage and variability issues loom large at 20nm and not all processes at this node are going to change the pitch as far as metallization is concerned. This means that there’s not necessarily going to be the same device shrinkage moving between nodes as there has been previously, he observed. “Do I actually get smaller chips when I move to this new node? That’s a little unclear at the moment until all that’s been fixed.”

When it comes down to it, there’s been a significant investment in terms of tools, IP and infrastructure by a lot of companies on 28nm, and they will certainly want to see a ROI on those investments. That will affect how long they stay at that node, and where they go next.