How To Optimize Silicon Utilization To Improve PPA

In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce performance.

On the other hand, particular PPA optimization prospects, such as wasted resources, might not require trade-offs. Underutilized, redundant components, which may not be optimized away by synthesis, might result in unnecessary power consumption without providing any functional value. These components waste resources and drain power. Yet, as designs grow more complex, containing millions of gates and billions of transistors, effectively detecting and eliminating these underutilized components becomes increasingly challenging.

Automatic design analysis: State of the art

Traditionally, structural coverage is used to identify unreachable, dead code, toggle, FSM, statement, branch and expression coverage. A lot of this analysis is clustered around unreachability analysis. If it is impossible to exercise a line of design code, or component expressions (or branches), with any stimulus, then that line of code or the relevant expression is unreachable. This can happen with branches such as if-then-else, muxes, flip-flops, etc. However, it is very possible that design code may be reachable, i.e., can be exercised in silicon with some stimulus. Still, the design logic may not drive any sound logic, making it redundant.

Therefore, area optimization and redundancy analysis shouldn’t be limited only to the scope of the unreachability analysis. This analysis should go beyond the structural coverage, uncovering the design’s reachable but redundant or partially redundant elements. Partial redundancy may result from a lazy design style, which can be optimized away early on if flagged on time. Partial redundancy may result from a lazy design style, which can be optimised away early on if flagged.

Area analysis of full silicon designs

footprint is Axiomise’s solution for area analysis, which automatically identifies underutilized resources without requiring the user to write any testbench, stimulus, or coverage. The tool is a part of the axiomiser, which is a versatile platform for formal verification solutions. We have brought our field experience of deploying formal for over two decades in the axiomiser platform.

It is reshaping how the industry looks at the problem of redundancy and methods of classifying unused components, making it a valuable tool during the design process.

How does the footprint technology work?

footprint detects redundancy by running formal property verification for component utilization. We classify components as fully redundant if they are not used anywhere in the design to drive any logic, or if we cannot use them; for example, we cannot fill up a FIFO. Although some of the utilization issues can be picked up through reachability analysis, for example, the FIFO cannot become full; partial utilization of such components is never done through any apps and is not even performed during functional verification through formal or simulation. For partial utilization, synthesis cannot always detect those cases. For example, a FIFO that only ever becomes 33% full will still be synthesized at maximum depth and will consume area and potentially dynamic power. We identified hundreds of issues in so many designs, where chains of flops are clocked and routed through to a multiplexer, where the logic values cannot be transferred across the multiplexer, exposing functional issues and PPA.

Table 1: Comparison of footprint with Lint and Coverage solutions.

We tested over 85 designs. A small set of footprint analysis results for the open-source designs is presented in the table below, highlighting the potential wasted gates and components in each design.

Table 2: footprint results on open-source designs, showing redundant components.

footprint integrates seamlessly with existing formal tools, offering flexibility and ease of use without requiring significant changes to the current workflow. Furthermore, its user-friendly, interactive interface enables a straightforward flow, allowing the easy regeneration of the results after the design changes. Features, such as precise measurement and reporting, not only permit designers to make informed decisions rapidly but also eliminate unnecessary complexity, ensuring that the results are clear, effective and relevant. Therefore, footprint ensures that no part of the design is ignored. It offers a deep analysis by identifying inefficiencies that are otherwise difficult to detect.

Conclusion

To support the vision of making formal normal, footprint was built as an automated solution that can be applied to practical designs as large as hundreds of millions of gates without facing a capacity issue. It brings all the benefits of formal verification, such as covering the entire state space, to the designers and architects as a push-button solution. footprint shrinks the time and mitigates the user expertise required to bring up a formal testbench. Zero experience in the field of formal verification is needed to use the tool, enabling engineers to focus on area and power optimizations from the first day of the new design cycle. Dealing with the issues from the start can lead to the overall efficiency of the chip design. Unutilized areas or even potential bugs can be discovered at an early stage, which can result in smoother and less painful mitigation of the issues, minimizing the impact of the changes. footprint may help speed up synthesis because the synthesis engine will not spend time on some redundancies caught early by footprint.