Huawei Delivers Outstandingly Accurate Models

By John Parry, Mentor, a Siemens Business, and Yake Fang, Huawei Technologies Co., Ltd.

Packaging high-performance multi-core IC devices used in communication applications is a key challenge for both manufacturers and system integrators. Traditionally a System-in-Package (SiP) has been taken, with chips mounted side-by-side, allowing differing semiconductor technologies to be mixed. More recently, stacking silicon die has become more commonly used as volumes have increased, making the System-on-Chip (SoC) design approach, which has much higher upfront non-recoverable expenditure, the cheapest option overall. These multi-heat source devices require very careful thermal design frontloaded in the design process, due to the very high cost of changes during detailed design.

The increased functionality and power dissipation has made the thermal design of communication device applications crucial in today’s increasingly high computing power communication device industry. These products present a very challenging thermal environment for our SoC packages, with the need to design to very tight thermal tolerances to meet size, weight and form factor goals.

Huawei always pays attention to thermal challenges in product design and uses thermal analysis throughout the whole product R&D phase. We have the ambitious program to develop an internal thermal design flow for multi-core SoC and SiP devices that would enable us to use the highest possible quality thermal data and models to facilitate our own design efforts.

We have used FloTHERM for almost 15 years, so we have a rich depth of experience and are able to create detailed thermal models of our SoC and SiP products. However, we needed a way to test that these packages achieved the ‘as-designed’ thermal performance, and to test packages from other suppliers rather than rely on their thermal data, which is often not sufficiently accurate or suitable for design. As it is based on the thermal transient measurement principle, giving the highest available fidelity, we turned to Mentor Graphics’ T3Ster hardware to perform a series of thermal tests so our thermal engineers could better understand the thermal impedance characteristics of these high performance products, and reduce time and resources needed to achieve a good design.

As a test vehicle for this new design workflow, we chose to investigate a 3-core SoC device typical of those now used in communication device applications and assembled in a Package-on-Package (PoP) format that allows package stacking. The FloTHERM model is shown in figure 1.

“To design successful communication devices, Huawei first performs thermal simulations in FloTHERM, and then calibrates the detailed thermal model based on accurate thermal measurement data obtained from T3Ster. In parallel with this Huawei optimizes the design through different material selection to decrease thermal resistance, confirmed using T3Ster’s transient thermal measurement. This process is much faster and requires fewer resources than we needed before, and provides Huawei with a highly-accurate thermal model to use in our system-level modeling, helping us get products to market faster than our competitors.” – Fang Yake, Senior Engineer, Huawei Technologies Co. Ltd.

As soon as the first working packages were produced, they were measured using Mentor Graphics T3Ster hardware, which records the temperature response of the part to a power step from just a few microseconds until steadystate is reached, with an accuracy of ±0.01°C.

Having creating the detailed numerical model of the package in FloTHERM, we performed a transient simulation to get a baseline result for this, as yet, uncalibrated model, which we built using the best available information during the design. The temperature vs. time graphs we got from FloTHERM and T3Ster seemed to match quite well.

Using a model of the package in the same thermal environment in FloTHERM allows the temperature vs. time response from the FloTHERM simulation to also be converted into a Structure Function, and then the two Structure Functions compared. This is a plot of the cumulative thermal capacitance vs. the cumulative thermal resistance that the heat experiences as it leaves the package. If the model exactly matches reality for the package, then the two Structure Function curves should match perfectly, as the heat flow paths from the die junction out to the environment should be identical.

We then post-processed this temperature vs. time data to create a Structure Function graph for the T3Ster and FloTHERM results, and compared these. We were not expecting an exact match, as there are always uncertainties surrounding material thermal properties. The thickness and uniformity of bond lines, and contact resistances within the structure where one material is not in perfect thermal contact with its neighbor materials. However, we were somewhat surprised at how big the differences were when we compared Structure Functions, as shown in figure 2. The Structure Function comparison is a very powerful tool for showing up differences between the model and the experimental result, and where those differences are in the heat flow path.

Figure 2 shows the Structure Functions for the initial FloTHERM simulation (black) vs. the T3Ster measurement data (blue), shown here when Core 1 is powered. The two Structure Functions are clearly quite different. At the far right of the plot the thermal capacitance becomes infinite, as heat reaches the environment. For the FloTHERM model this occurs at a lower thermal resistance than found in practice, so the model is underestimating the temperature rise. Some of this difference may be due to deficiencies in the way the cold plate is modeled. However, the differences seen on the left of the graph are within the package model itself, and close to the heat source. Simulation vs. test results, when cores two and three are powered, both showed similar discrepancies.

To modify the model manually to bring it in line with the experimental results would be very time consuming and error prone as it would be a guess-and-correct process that is impractical to undertake a fast-paced design environment like ours. However, part of our reason for choosing T3Ster is that its results can be read into FloTHERM’s Command Center tool, which allows automatic calibration of multiple user-selected parameters to adjust the model to match the measurement data. This calibration gives a very good fit, something that would be extremely difficult and time consuming to do manually, and so results in a model that has very high accuracy for us to use in system design.

To do this automatic calibration, we selected the time range corresponding to heating within the package, ignoring the part of the curve that represents heating of the board and the cold plate, so truncating the transient calculation to 0.15 s. The optimization requires a list of parameters, the exact values of which are uncertain, and a possible range for their thermal conductivity values. The parameters selected were the C4 bumps, with a conductivity ranging from 40 W/mK to 70 W/mK; the underfill (0.2 W/mK to 0.7 W/mK; the package substrate (10 W/mK to 20 W/mK); and the solder mask (0.5 W/mK to 3 W/mK).

The result, shown in figure 3, gives an excellent match within the thermal resistance range up to the junction-to-board thermal resistance (RthJB). This has proved to us the effectiveness of FloTHERM’s auto calibration technology coupled with T3Ster, and the calibrated model can be used for board-level and system-level thermal analysis with a very high degree of confidence in the fidelity of the results.