Hunting For Macro Defects: The Importance Of Bare Wafer Inspection

As logic and memory semiconductor devices approach the limits of Moore’s Law, the requirements for accuracy in layer transfer become increasingly stringent. One leading silicon wafer manufacturer estimates that 50% of epitaxial wafer supply for logic will be on nodes equal to or less than 7nm. This is up approximately 30% from earlier in the decade.

To meet the demands of extreme ultraviolet (EUV) lithography, these leading-edge epi-deposited substrates have tighter specifications than previous substrates. Consider 3-5nm logic nodes: the image placement requirement can be as low as 3nm [1].

With the more stringent requirements of EUV lithography in mind, wafer makers are searching for new solutions, such as those addressing the primary reason for inaccuracies in image transfer: macro defects.

Even in ultra-clean class 10 environments, macro defects — like macro particles, polishing-related scratches, and multi-faceted pits — can be found on and, at times, be created on wafers, causing the next process layer to be misaligned. This is especially true during the process steps following single-crystal wafer ingot growth and wafer-making, steps that include sawing the ingot to produce wafers, lapping, etching, polishing, and cleaning. During these steps, the possibility for the generation of defects is increased, with each one potentially resulting in killer defects leading to yield loss. In the case of surface pits on a wafer, evidence ties them directly to bad memory cells and the complete destruction of the memory device located at the pit.

In regards to macro particles, their presence on the wafer backside can cause problems with electrostatic chucking, which leads to localized hotspots. Given the fact that frontside processes such as etching or deposition are extremely sensitive to surface temperature, such hotspots can result in local process non-uniformity.

In addition, macro particles can accumulate on the wafer backside during chucking or in interactions with robot end-effectors during wafer movement. These macro particles can also fall onto the frontside of the wafer, leading to further killer defects and resulting in yield loss.

As for polishing-related scratches, chips, and pits on the edge of the wafer, each one can result in a high stress point on the pristine crystalline structure (figure 1). During the thermal processes the wafer undergoes, scratches, chips, or pits can become nucleation sites for significant stress buildup. If these stresses are large enough, they can break the crystalline wafer, leading to a total loss of the wafer and a significantly contaminated process chamber.

Fig. 1: Chip at the wafer edge; this can become a high stress point for subsequent process steps.

Wafer backside haze is typically seen as a nuisance measurement but can sometimes reveal issues during wafer processing. High backside haze can show pin marks or susceptor marks after a thermal process which may have led to localized thermal non-uniformities, so it is important to accurately measure and then interpret this haze.

All of these are reasons why it’s increasingly important that bare wafers are thoroughly inspected for macro particles, pits, scratches, and chips on all surfaces after the wafer has been manufactured and before the first epitaxial silicon growth step is taken. Once these defects have been identified and enumerated, active algorithms can be implemented to immediately reject high-risk wafers. Equivalently, identifying and classifying all macro particles and defects accurately can prevent unnecessary false rejections, another factor that can increase costs.

Adding to these bare wafer challenges: wafer manufacturers are projecting, for the foreseeable future, supply constraints for 300mm polished and epitaxial wafers. To avoid scrapping resources that are in short supply or conducting additional time-consuming rework on these wafers, accurate predictions of wafer quality become even more important than before.

Fortunately, new cost-effective inspection technologies are available to address these challenges. By using these tools, wafer makers can improve overall wafer quality, reduce costs, and increase productivity. Employing both bright field and dark field methodologies, laser-based or white-light based optical scatterometry can be used to inspect bare polished wafers and epitaxial layers. When combined with complex algorithms like those in automatic defect classification (ADC) software, such integrated technological innovations can potentially become indispensable tools for wafer manufacturers.

Along with wafer makers, integrated device manufacturers (IDMs) can also benefit from bare wafer inspection. Because transporting wafers from the wafer facility to the IDM fab can lead to the generation of macro particles, IDMs may choose to deploy a second round of wafer inspection using this set of technologies.

Similarly, these same tools can be applied to the manufacture of compound semiconductors. In this market, these technologies can be used to inspect silicon carbide (SiC) or gallium nitride (GaN) for surface macro particle defects, a potentially yield-improving move considering that studies have shown that defect analysis can be directly correlated to wafer yield on SiC device wafers [2].

Given all of these factors, it’s clear that edge, back and notch inspection for macro defects is an important investment for wafer makers to prevent excessive loss on the one hand and guarantee outgoing wafer quality on the other. This unique type of defect analysis is important for IDMs to ensure that only the best incoming wafers are used for applications like logic, memory, and power, which need the most stringent lithography requirements.

[1] L. Peters “How Overlay Keeps Pace With EUV Patterning,” Semiconductor Engineering, August 9, 2022

[2] H. Das, et al. “Effect of Defects in Silicon Carbide Epitaxial layers on Yield and Reliability”, Mat. Sci. Forum, Vol. 963, pp 284-287.