Q1 2019 Unit Drop Impacts Wafer Demand For 2019


The Semico Wafer Demand Model update for Q1 2019 now results in a 5.9% decline in wafer demand for 2019. Along with process technology and productivity, Semico’s Wafer Demand Model is highly dependent on semiconductor unit sales. In the Q1 2019, total semiconductor units dropped by 7.4% compared to Q4 2018 and 3.8% compared to Q1 2018. The drop in units is significant because of the broad spe... » read more

From Sand To Wafers


More than most industries, ours is identified with a single element, silicon. Consider the self-adopted naming conventions of all the places that want to be recognized as members of the club—Silicon Valley, Silicon Beach, Silicon Forest and so on. Silicon wafers are fundamental in manufacturing the electronic “chips” that pervade almost every aspect of our lives. New applications in IoT, ... » read more

150MM Alive and Kicking


Did you think chip making on 150mm wafers was a thing of the past? Think again. Many of the megatrends shaping our collective futures—mobility, autonomous driving and electric vehicles, 5G wireless communications, augmented- and virtual reality (AR/VR), and healthcare—depend on innovations created on the 150mm wafer size. While attention is often riveted on the race to the leading-edge n... » read more

Inspecting Unpatterned Wafers


Unpatterned wafer inspection, which has flown well under the radar for most of the semiconductor industry, is becoming more critical amid the need to find defects earlier in the manufacturing process flow. Finding those defects is getting harder as critical dimensions shrink. It's more difficult to actually detect smaller defects on bare wafers, there is more data to process, and there is mo... » read more

All I Want For Christmas…


As I write this, we’re heading into the 2016 holiday season. December 21 is also the shortest day of the year, so I better get right to the point. 2016 has been a year of many surprises. The spectacular consolidation in the semiconductor industry has permanently altered the landscape.  It has created new, world-class capability and left a few gaps as well. 2.5D designs are finally moving ... » read more

The Week In Review: Manufacturing


Fab tools Is Nikon’s semiconductor lithography equipment business on the ropes? Amid losses and dwindling market share, the company has announced a major restructuring plan for this unit. It will reduce fixed costs related to its 193nm immersion scanner business “by headcount rationalization and re-assignments of 1,000 employees,” according to Nikon. In addition, Nikon is reassessing its... » read more

Over 65% Smartphone RF Switches SOI, Says Yole; Power Amps Next


By Adele Hars The industry research firm Yole Développement says that more than 65 percent of substrates used in fabricating switches for handsets are SOI-based. This is a high-growth part of the market, putting up double-digit increases. Like a standard SOI wafer, an RF SOI substrate has an active (“top”) layer on which CMOS transistors are built, with an isolating (“BOx”) ... » read more

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP


Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

Bigger Wafers, Bigger Risk


At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

FinFET Isolation: Bulk vs. SOI


Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

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