Power/Performance Bits: June 28

Making uniform wafers; GaN-based CMOS circuits; tunable on-chip photonic interface.


Making uniform wafers

Scientists from the Korea Institute of Machinery & Materials (KIMM) and Nanyang Technological University Singapore (NTU Singapore) propose a technique that combines nanotransfer printing with metal-assisted chemical etching to improve wafer uniformity and increase yield.

The researchers used a chemical-free nanotransfer printing technique that transfers gold nanostructure layers onto a silicon substrate at low temperature (160 °C) to form a highly uniform wafer with nanowires that can be controlled to the desired thickness during fabrication. The team said that the printing technique works by triggering direct chemisorption of the thin metal films under heat, a chemical reaction that creates a strong bond between a substrate surface and the substance that is adsorbed.

The technique is compatible with industrial processes and allows a wafer to be fabricated quickly and uniformly at scale, from nanometers to inches. In addition, the researchers found that the fabricated wafer is almost defect-free. In lab tests, the team was able to achieve more than 99% yield transfer of a 20-nanometer thick Au film onto a six-inch Si wafer. This printable wafer size was limited to the laboratory setup, and the team believes their technique can easily be scaled up for use on a twelve-inch wafer.

When the method was adopted to fabricate a six-inch wafer, the printed layer remained intact with minimal bending during etching. Photodetectors fabricated on the wafer showed uniformity of performance.

“The technique devised by the research team from KIMM and NTU has proven to be effective in creating wafer with excellent uniformity, which translates into fewer defective semiconductor chips. The reality of global chip supply is its vulnerability to many external factors, including shortage of materials and unexpected events like the supply chain disruptions caused by the COVID-19 pandemic. Our newly developed method thus has great potential to relieve the tension on the global chip supply in future by increasing chip yield. Moreover, chip makers may also enjoy greater cost-efficiency with higher yields,” said Munho Kim, an assistant professor from the School of Electrical and Electronic Engineering at NTU.

The research team has filed for patents in Korea and Singapore. Next, they are aiming to scale up their technique with an industrial partner for commercialization within the next few years.

GaN-based CMOS circuits

Researchers from the Hong Kong University of Science and Technology developed gallium nitride (GaN) based CMOS logic circuits that could have the potential to cut the power consumption of the logic control unit in conversion power systems by 20-30%.

“We analyzed the theoretical speed limit and energy efficiency of GaN CMOS technology, based on the material properties of GaN and the readily available fabrication techniques on 8-inch lines. We found that the single-stage logic gate delay, even with a relatively pessimistic estimation, can be shorter than 1 nanosecond through process optimization and device down-scaling for GaN CMOS circuits on commercial platforms,” said Kevin J. Chen, chair professor in the department of electronic and computer engineering at HKUST.

“Although this is still slower than the state-of-the-art, high-speed CMOS circuits, it comfortably meets the requirements of GaN-based power conversion systems, whose operating frequency generally does not exceed 10 MHz.”

Chen added, “With GaN-based CMOS circuits implementing peripheral circuits such as controller, driver and miscellaneous sensors, the power dissipation of logic blocks can be substantially reduced by more than 3 orders of magnitude. As a result, the overall power consumption of the logic control unit in power system can be reduced by 20-30%. Downscaling and gate stack engineering of p-FETs are expected to further improve the performance and accelerate the commercialization pace of GaN CMOS logic circuit technology.”

Tunable on-chip photonic interface

Researchers from the University of Chicago developed a tunable on-chip photonic interface that can guide light in one direction by coupling light confined in a nanophotonic waveguide with an atomically thin, two-dimensional semiconductor.

The team used the two-dimensional material tungsten diselenide. “The unique properties of the material’s band structure enables it to interact with light differently based on the helicity of the light’s polarization. In nanophotonic structures, where light is confined below its wavelength, circular polarization arises naturally, and the helicity is locked to the light’s propagation direction,” the researchers noted.

Light emitted from the tungsten diselenide will couple into the waveguide in a preferred direction. This can also be switched on and off by adding electrons to the system, creating a tunable emission router.

“We’ve figured out a scalable method for putting photonics and 2D semiconductors together in a way that adds new control knobs and preserves the high quality of the sensitive material,” said Robert Shreiner, a graduate student at University of Chicago. “This interface opens new doors for designing ultra-compact, one-way photonic devices.”

The researchers said the device could be used to help integrate photonic elements into existing optoelectronic system, such as on-chip lasers for lidar. “We see this research as paving the way towards a whole new class of integrated photonic circuits,” said Alex High, an assistant professor at University of Chicago.

Kai Hao, a postdoctoral fellow at University of Chicago, added, “We already use photonics to carry information throughout the country in fiber-optic networks, but advances like this could help fully control the flow of light on the nanoscale, thus realizing on-chip optical networks.”

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