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Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography

A study looks at the feasibility of finding intra-wafer distortion wafer-by-wafer.

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Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this paper, the capability to do this is evaluated in a feasibility study.

Authors:
From United Microelectronics Corp. (Taiwan) — Jia Hung Chang, En Chuan Lio, Junjin Lin, Tang Chun Weng, and Bill Lin.
From Qoniac GmbH (Germany) Patrick Lomtscher, Martin Freitag, and Stefan Buhl.
From Qoniac Taiwan Ltd. (Taiwan) — Hsiao Lin Hsu and Rex H. Liu.

Abstract from SPIE. Click here to read full abstract and access article (for a fee).

 



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