Hyperconvergence Of Design For Test And Physical Design

By Sri Ganta and Hyoung-Kook Kim

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implementation tools to have tighter integration with DFT tools to manage the intricacies of different structures of DFT logic.

One of the key components of the DFT logic is the scan data compression technology, which is now widely used in most of the large designs.  Along with an increase in size and complexity of designs, the size of the scan compression logic also increases, primarily to reduce the test data volume and test time, which in turn reduces the test costs. Hence the scan compression logic must be optimized for both logic and physical placement to provide the best PPA. Synopsys TestMAX DFT product offers DFTMAX, DFTMAX Ultra, and DFTMAX SEQ compression technologies, to suit different design requirements.

In general, logical and physical optimization mainly focuses on enhancing functional logic to improve PPA. However, the implementation of DFT compression logic connecting to scan chains can lead to challenges. When scan chains are configured to connect to DFT compression logic, the end scan registers of the chain can be located at different physical locations. Without any placement constraints on the DFT compression logic, it is placed at the center of design core area. As shown in fig. 1, this central placement leads to routing congestion, as all scan chain connections converge to the DFT compression logic at the center, impacting the core functional PPA.

Fig. 1: Left: scan chain connections. Right: cell density map.

Synopsys Fusion Compiler solves the challenge by using the following innovative procedures, including RTL design restructuring of DFT compression IP, logic optimization, and physical optimization.

1. Physical-friendly DFT compression RTL generation
   DFT compression logic is re-structured in RTL by splitting into several sub blocks. Tool analyzes the size of design and determines the size of sub blocks.
2. Area-based and congestion-based logic optimization
   Logical optimization of DFT compression logic helps reduce entanglement between sub blocks of DFT compression logic.
3. Physical-aware scan chain clustering with consideration of DFT compression logic
   Physical information of scan chains is used to cluster scan chains and assign clusters to sub blocks of DFT compression logic.
4. Physical placement of DFT compression logic
   Physical placement engine analyzes the connection between scan registers and DFT compression logic and applies constraints to place DFT compression logic near to scan registers without sacrificing functional PPA.

Through the comprehensive solution, DFT compression logic is distributed throughout the core area and the routing resource of the center can be utilized for achieving best-in-class PPA for the overall design.

Fig. 2 below illustrates the DFT compression logic split into smaller blocks, physically distributed and connected to the local scan-chain clusters.

Fig. 2: Distribution of DFT compression logic based on physical placement.

As shown in figure 3, distributing DFT compression logic physically across the design area brings benefits for all aspects of PPA, such as reduction on cell instances, routing congestions, wire length, and more.

Fig. 3: Improvements in several aspects impacting PPA.

In conclusion, this article highlights how DFT compression logic can be optimized by interweaving the Synopsys TestMAX DFT and Fusion Compiler technologies to achieve best-in-class PPA. Synopsys TestMAX products are integrated not only with physical design but also with EDA tools and IP across product portfolios, including verification, power signoff, timing signoff, and Silicon Lifecycle Management. Synopsys is uniquely positioned to provide unprecedented competitive advantage to our chip-design customers by leveraging tighter integration among the EDA tools across the RTL 2 GDS flows – an initiative we call “hyperconvergence.”

References

1. Improving PPA With AI
2. Understanding Power, Performance, and Area (PPA) Analysis in VLSI: Key to Efficient Chip Design | LinkedIn

Hyoung-Kook Kim is a principal engineer at Synopsys.