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Improving Automotive Reliability

Signoff requirements for next-gen automotive electronics.

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Semiconductor reliability requirements are rapidly evolving. New applications such as ADAS/self-driving cars and drones are pushing the limits for system reliability.

A mobile phone that overheats in your pocket is annoying. In automobiles, it’s a much different story. Overheating can impact the operation of backup sensors, which alert the driver that a pedestrian or obstacle is behind them.

According to the NHTSA, 94% of the 6.3 million automotive accidents that occurred in the United States in 2015 were caused by human error, resulting in 35,000 deaths. (Traffic Safety Facts Research Notes, NTSA, August 2016, February 2015). The good news is that safety features that were available only in high-end luxury cars a few years ago now are becoming either standard or options in most new cars.

But the safety and reliability of automotive systems are only as good as the electronics inside of them, something that will become even more apparent as the volume of electronic content inside vehicles continues to rise. We are moving from an automotive market with almost no automation to full automation. The number of cameras and sensors is growing rapidly, and so are the needs for faster processing speed and improved image quality.

Moreover, these systems must learn on the fly and make decisions at lightning speed. Unlike traditional applications, where a system can be pre-programmed to follow a set of rules to arrive at a decision, autonomous vehicles require artificial intelligence, which needs immense training to respond to a myriad of situations in real time, such as pedestrian detection in poorly lit areas and bad weather. The amount of data that needs to be sensed and processed is exploding, and automotive applications need to comply with stringent safety requirements to engage in this game.

To make all of this work, automotive companies need stay focused on issues that may be new to this market:

Electromigration
The complexity of the process technology and interconnect is increasing significantly with each progressive technology node. An increasing number of GDS layers, growing complexity of design rules, and rising interconnect resistance coupled with faster switching speed significantly increases the number of EM violations. These EM violations are harder to evaluate and fix due to narrower widths. Design teams spend a lot of time and effort in evaluating EM violations during signoff to determine if it can be waived or not. Machine learning approaches are being leveraged to perform EM waivers, as it is becoming a very resource-intensive exercise. Automation that makes use of historical EM waiving experience for new designs can emphasize must-fix EM violations, and it is far less error-prone than manual methods. It significantly helps in reducing false EM violations.

Thermal Reliability
For N16/N7, the increased functionality and higher current densities in SoCs can cause localized self-heating of devices and joule heating of wires, leading to a large variation of temperature across the chip based on different modes of operation. Higher temperature, higher current and higher resistances are pushing the limit for electromigration (EM) and electrostatic discharge (ESD) failures on chip. For certain mission-critical applications such as air-bag deployment devices, ambient temperature of the chip can affect the transient behavior.

In addition, advanced 2.5/3D and wafer-level packaging technologies are bringing the die and wafer together. This creates more thermal hot spots, which will impact both the chip and system level EM and ESD. It also can increase the chance of thermal-induced stress, which can lead to warping and contact separation. Those, in turn, can result in long-term reliability issues that ultimately will render the product useless. A comprehensive solution is necessary to address chip-level thermal analysis and chip-aware system-level thermal analysis to achieve thermal integrity and power-thermal convergence across the spectrum of chip, package and board.

Statistical EM Budgeting
Statistical Electro-Migration Budgeting (SEB) allows chip designers to meet the stringent safety and reliability requirements by prioritizing the most important EM fixes for signoff while avoiding over-design. With increased temperature variation across the chip in finFET-based designs due to device self-heating and joule heating of the wires, the number of EM failures increases significantly. Hence, SEB becomes critical to prioritize EM fixes. Designers can benefit greatly from SEB modeling by fixing only the top few percent of the total number of EM violations identified to be critical for product reliability.

Electrostatic Discharge
With prominent use of IPs in high-speed I/Os and SoC peripherals, ESD verification is becoming critical. It is now one of the sign-off criteria. Typical issues caused by ESD are device breakdown, interconnect meltdown and cross-domain problems. The ESD window is shrinking with each new node, and conventional approaches such as DRC checks are no longer sufficient for signoff. What is needed is a simulation-based approach that can detect connectivity, resistance and current density from early in the design cycle to signoff. With decreasing oxide thickness, ESD schemes used in one technology are not guaranteed to work in the next. ESD robustness per area varies a lot between foundries and different layout structures, even for the same technology node. In addition, the increase in resistance, current densities, associated joule heating, as well as the use of ultra-thin gate oxides directly impact ESD robustness.

Almost 55% of the failures are interconnect-related and can be avoided by performing systematic ESD checks during design phase. But ESD protection that works at the IP level may not work at the SoC level due to poor connectivity to other IPs and circuits in the SoC. Therefore, it is important to analyze the ESD protection schemes at the SoC level across multiple voltage domains to make sure they provide the intended low resistance path to discharge a potential ESD event without stressing the functional devices.

In upcoming ANSYS webinars, learn how simulation can address a broad swath of issues that will come into play in the automotive market, including analog/mixed signal, reliability analysis, low power and thermal issues.



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