Improving DRAM Performance Using Dual Work-Function Metal Gate (DWMG) Structures

Dynamic Random Access Memory (DRAM) serves as the backbone of modern computing, enabling devices ranging from smartphones to high-performance servers. As the demand accelerates for higher density and lower power consumption in memory devices, innovation in reducing DRAM leakage currents and enhancing performance becomes essential.

One significant challenge in scaling DRAM technology is gate-induced drain leakage (GIDL), a primary source of standby charge loss. This article explores how a Dual Work-Function Metal Gate (DWMG) structure in DRAM buried word-line (BWL) can mitigate GIDL. By leveraging a full-scale process integration model that supports electrical analysis, we demonstrate how this approach reduces leakage current while maintaining robust device performance.

The challenge of GIDL in modern DRAM

GIDL is primarily caused by band-to-band tunneling (BTBT) at the drain junction under high electric field conditions. This phenomenon not only increases off-state leakage currents but also degrades memory state retention time in DRAM cells, particularly as feature sizes shrink below 20 nm.¹

Factors such as thinner gate oxides and higher doping concentrations exacerbate GIDL, creating a synergistic effect that makes it a critical problem in designing low-power, high-density DRAM.²

Fig. 1: (a) Gain-induced drain leakage during pre-charge mode in DRAMs and (b) the mechanism of trap-assisted band-to-band tunneling.³

The solution

The introduction of a dual work-function metal gate structure provides a compelling solution to this challenge. By segmenting the buried word-line gate into regions with distinct work functions, the electric field along the channel is precisely controlled. Examples of some dual work-function metal gate structures are shown in figure 2.

This structure suppresses BTBT generation, thereby reducing GIDL without compromising drive current or threshold voltage (Vt). As a result, this design is well-suited for advanced DRAM nodes.^4,5

Fig. 2: (Left to right) U.S. 9,543,433 B2 Samsung Patent,⁴ U.S. 9,543,433 B2 Micron Patent,⁵ and U.S. patent 9,276,114 TSMC patent.⁶

DWMG alignment with industry trends

The DWMG approach aligns with broader semiconductor trends emphasizing advanced gate designs and channel engineering. Our study applies this innovation to DRAM technology, addressing GIDL challenges while preserving key performance metrics. Similar methods have been successfully implemented in finFETs⁶ and tunnel FETs⁷ to reduce leakage and improve subthreshold slopes.

Leveraging process integration modeling for insights

Our process integration modeling platform (SEMulator3D) with built-in electrical analysis capabilities played a pivotal role in evaluating the DWMG design. This tool allowed us to:

1. Simulate the full process flow of a DRAM cell array, from active area formation to capacitor integration (figure 3a).
2. Focus on the BWL transistor by extracting and refining a specific transistor for electrical characterization (figure 3b–d).
3. Analyze the interactions between process parameters—such as gate work-function, oxide thickness, and doping profiles—and their impact on electrical performance.

This simulation framework provided a holistic view of integration challenges and revealed the effectiveness of DWMG in reducing current leakage.

Fig. 3: The full process integration of a DRAM cell array: (a) The whole structure up to the capacitor top TiN deposition, (b) a top-down view to define the desired cross-section, (c) a zoomed view of the cell BWL transistors from which a target transistor is cropped, and (d) an electrical simulation structure of a cropped BWL transistor with the doping profile.

DWMG design and simulation results

The DWMG structure is realized by splitting the gate into upper and lower regions with distinct work functions in the upper region’s metal gate of 3.5eV, 4.1eV, and 4.7eV (figure 4). The device simulation considers the models of doping/field-dependent mobility, Shockley-Read-Hall (SRH) generation/recombination, and trap-assisted band-to-band tunneling effects.

The drift-diffusion equation is solved to obtain I_drain vs. V_gate curves, both in the linear and saturation regimes. The substrate current is measured (virtually) to determine the GIDL leakage amount.

Fig. 4: A cross-section of the device simulation structure and metal gate work-function split conditions.

Key results include the following:

1. Leakage reduction (figures 5a and 5b): The low and high work-function regions, in the upper gate and lower gate, respectively, create a more relaxed electric field distribution than the same work-function without the DWMG, which suppresses BTBT at the drain junction and in turn reduces leakage current.

Fig. 5: Electric field and BTBT rate at the gate-drain overlap region (left) and a 2D field view of BTBT rate at Vg=-2.5V and Vd=+1.5V bias conditions (right).

2. Preserved device performance (figure 6a–c): Despite the GIDL reduction (I_subtrate), critical IV characteristics in both linear (Idlin_Vg) and saturation (Idsat_Vg) regimes remain intact when using the DWMG, ensuring reliable operation during read and write cycles.

Fig. 6: Id vs. Vg in linear regime @Vd=0.1V (left), Id vs. Vg in saturation regime @ Vd=1.5V (middle), and Isub vs. Vg @Vd=1.5V (right).

3. Process dependency (figure 7a and 7b): Gate oxide thickness and doping concentration significantly influence performance. For instance, thinner oxides improve field control but increase BTBT risk due to the reduced barrier width. Similarly, higher doping improves modulation capabilities but exacerbates BTBT by increasing the electric field intensity, which accelerates tunneling processes.

Fig. 7: Isub and max BTBT rate vs. gate oxide thickness (left) and Isub and max BTBT rate vs. source/drain doping (right).

Advantages of combining device electrical analysis with process integration modeling

Performing device electrical analysis during process integration modeling can enable the following types of advanced analyses that identify design-technology trade-offs:

• Electrical pathfinding: This type of analysis can be used to rapidly explore combinations of gate work-functions, oxide thicknesses, and doping profiles to pinpoint optimal designs. This approach has the potential to minimize the cost and time of physical experiments while reducing risks associated with late-stage failures.
• Variability analysis: Statistical simulations can identify the impact of process variations—such as gate oxide non-uniformity and doping fluctuations—on GIDL and IV characteristics. This type of analysis highlights critical design margins and has the potential to provide feedback on process optimization (such as active area formation) from very early process development stages.

The future of DWMG and DRAM

The dual work-function metal gate (DWMG) is a robust, scalable solution for mitigating GIDL in DRAM technology. By optimizing the electric field distribution, this design effectively reduces leakage currents while maintaining critical IV performance. Process integration modeling combined with electrical analysis capabilities is instrumental in demonstrating the ability to reduce leakage current using DWMG, offering a comprehensive framework for addressing design and integration challenges.

Future research efforts could include:

• Integrating DWMG designs with high-k dielectrics or advanced junction engineering to further enhance leakage control.
• Assessing the impact of scaling trends, such as smaller metal pitches and EUV lithography, on DWMG performance.
• Developing predictive models for variability in advanced DRAM nodes.

References

1. S. K. Gautam, et al, “Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM,” 2016 IEEE 8th IMW, Paris, France, 2016, pp. 1-4
2. J. D. Plummer, M. D. Deal, and P. B. Griffin, “Silicon VLSI Technology: Fundamentals, Practice and Modeling,” Prentice Hall, 2000.
3. Dae-Hyun Kim, Soonyoung Cha, Linda S. Milor, “AVERT: An elaborate model for simulating variable retention time in DRAMs”, Microelectronics Reliability, Volume 55, Issues 9–10, 2015, Pages 1313-1319, ISSN 0026-2714.
4. US patent 9,543,433 B2 Dual work function recessed access device and methods of forming
5. US patent 8,012,828 B2 Recess gate transistor
6. US patent 9,276,114 B2 FinFET with dual work function gate structure
7. Goyal, P., Madan, J., Srivastava, G. et al. Performance Analysis of Drain Pocket Hetero Gate Dielectric DG-TFET: Solution for Ambipolar Conduction and Enhanced Drive Current. Silicon 14, 8097–8107 (2022).