Determining the optimal way to perform deposition/etch cycling and improve critical dimension uniformity.
Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this study, we will demonstrate how virtual fabrication can provide guidance on how to perform deposition/etch cycling in order to reduce LER [4].
A typical line and via array pattern with a pitch of 40 nm was established as a test structure in the virtual fabrication software. Pattern critical dimensions (CD) and LER amplitude and correlation length (measures of line edge roughness) were then explored under different experimental conditions.
Fig. 1: The virtual process flow of a deposition/etch cycle process used to improve LER. Figure 1 (a-c) 3D view, (d-f) top view of the incoming structure after deposition and etch cycling.
A deposition/etch cycling process was applied in a virtual model to improve the line edge roughness (LER) and critical dimension uniformity (CDU) of the pattern (figure 1). Virtual metrology was used to measure LER standard deviation (LERSTD), LER correlation length (C) and Via CD range (VCDR) to evaluate the impact of the selected process changes on LER and CDU improvement.
We ran 1500 virtual experiments using the incoming pattern CD, LER amplitude (A), LER correlation length (C), etch/deposition amount (THK), and number of deposition/etch cycles (NC) as experimental variables. Part of the results of our experiment are shown in figure 2.
Fig. 2: LERSTD/VCDR/CL vs deposition thickness and # of cycles at different incoming LER A/C conditions.
Figure 2 shows the trend in the Via CD ranges (VCDR), LER standard deviation (LERSTD), and LER correlation length (C) values with respect to the number of deposition/etch cycles (bottom axis) at different LER A and LER C conditions (top and right axis). Our goal is to minimize VCDR, LERSTD and CL values at the lowest number of deposition/etch cycles. We can draw three conclusions from figure 2.
Fig. 3: LER/VCDR improvement at the first cycle with respect to deposition thickness and CL for different incoming LER A.
As we mentioned earlier, most of the LER improvement happened in the first deposition/etch cycle, with the remaining deposition/etch cycles producing a much smaller improvement. Contour plots displaying the LER/VCDR improvement on the first cycle were fitted and illustrated in figure 3. From figure 3, we can draw two conclusions:
In this study, a deposition/etch cycling process was simulated to improve LER and CDU performance at advanced nodes by virtual fabrication. The results indicate that most of the LER/VCDR improvement seen during deposition/etch cycling processes occurred during the first deposition/etch cycle. The deposition/etch cycling process is very effective in reducing high frequency noise (when there is a smaller LER correlation length). LER improvements are larger at the via patterns than at the line patterns when a thicker film is deposited, exhibiting as larger LER correlation length values and lower LER amplitude. These results provide quantitative guidance on the optimal selection of deposition/etch amounts and the number of cycles needed, to both reduce LER and lower defects and variability in the production of advanced semiconductor devices.
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