A new technical paper titled “Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling” was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions.
Abstract:
“Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around nanosheet FETs. Trade-off between short-channel effects (SSAT), external resistance (REXT), effective capacitance (CEFF including parasitic capacitance CPARA) favors for a more aggressive outer-LG scaling (reduces CPARA and/or relaxes contact length, LCNT) keeping inner-LG relaxed (controls REFF, SSAT). Up to 10% speed-at-iso-leakage and speed-at-iso-power, and 15% power-at-iso-speed gains are possible with this unique design available in GAA-NS based devices, allowing for multi-node GAA extension without scaling more fundamental geometry parameters like thickness of NS.”
Find the technical paper here. November 2024.
K. K. Bhuwalka et al., “Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling,” in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2024.3492722.
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