Embedded FPGAs may be known for their flexibility, but specific optimizations open up new possibilities.
eFPGA adoption is accelerating.
eFPGA is now available from multiple suppliers for multiple foundries and on nodes including 180nm, 40nm, 28nm, 22nm, 16nm, 12nm and 7nm. There are double-digit chips proven in silicon by multiple customers for multiple applications. And many more in fab, in design and in planning.
The three main applications are:
In the early days of eFPGA, customers were experimenting and were at most willing to commit to one chip and wanted to keep their out-of-pocket costs low in order to give eFPGA a try.
So Flex Logix’ initial eFPGA offering was designed to easily support a wide variety of logic and DSP requirements and be able to deliver just the right size eFPGA that customers needed within days. We designed a 4K LUT tile (with a DSP version that replaced 1K LUTs with 40 DSP MACs); and designed the tile to be arrayable into large arrays of up to 7×7, 8×8, etc. Because of the wide range of process choices chip architects have now, we chose a design methodology that enabled us to be able to port our eFPGA to any process node in 6-8 months with a handful of engineers – so we could meet customer schedules and budgets.
This approach has worked and has resulted in a lot of adoption.
We now have some customers planning to do dozens of chips in a process node. And others planning families of chips with very high volume.
Increased adoption means the revenue that can be generated from a design/port is larger and the amount of engineering investment that can be justified goes up as well.
What are some of the possibilities?
The easiest eFPGA to design has no power management. And most initial customers for eFPGA have wanted “always on, fast as possible.”
For power sensitive customers it is possible to do many optimizations
We have implemented several different power optimized eFPGA implementations for customers already.
eFPGA, like FPGA chips, use bitcells to program the array and flip flops to hold state.
Both are susceptible to soft errors, just like microprocessors and ASICs. These errors are infrequent and most customers ignore them.
But there are some applications where very high reliability is required, for example autonomous vehicle control systems, space applications and some medical applications.
Scrubbing is an option for increasing reliability which is possible with standard eFPGA. If this is not sufficient, there are two other options:
Both of these approaches increase area, but if reliability is a must, they can be implemented. And we have done so for multiple customers.
For very high volume applications there are options to consider to reduce the area of eFPGA.
Here are a few:
eFPGA adoption is taking off. As customers plan dozens of chips on a node or very high volumes, the economics allow consideration of a range of optimizations to better shape the eFPGA to maximize their SoC’s value proposition.
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