Increasing eFPGA Adoption Will Shape eFPGA Features/Benefits

Embedded FPGAs may be known for their flexibility, but specific optimizations open up new possibilities.


eFPGA adoption is accelerating.

eFPGA is now available from multiple suppliers for multiple foundries and on nodes including 180nm, 40nm, 28nm, 22nm, 16nm, 12nm and 7nm. There are double-digit chips proven in silicon by multiple customers for multiple applications. And many more in fab, in design and in planning.

The three main applications are:

  • Integration of existing FPGA chips into SoCs to improve power, performance and cost
  • Enabling flexibility and customization for SoCs to handle changing interfaces and algorithms
  • Acceleration of key workloads where the parallelism of FPGA outperforms processors

In the early days of eFPGA, customers were experimenting and were at most willing to commit to one chip and wanted to keep their out-of-pocket costs low in order to give eFPGA a try.

So Flex Logix’ initial eFPGA offering was designed to easily support a wide variety of logic and DSP requirements and be able to deliver just the right size eFPGA that customers needed within days. We designed a 4K LUT tile (with a DSP version that replaced 1K LUTs with 40 DSP MACs); and designed the tile to be arrayable into large arrays of up to 7×7, 8×8, etc. Because of the wide range of process choices chip architects have now, we chose a design methodology that enabled us to be able to port our eFPGA to any process node in 6-8 months with a handful of engineers – so we could meet customer schedules and budgets.

This approach has worked and has resulted in a lot of adoption.

We now have some customers planning to do dozens of chips in a process node. And others planning families of chips with very high volume.

Increased adoption means the revenue that can be generated from a design/port is larger and the amount of engineering investment that can be justified goes up as well.

What are some of the possibilities?

Power optimized eFPGA

The easiest eFPGA to design has no power management. And most initial customers for eFPGA have wanted “always on, fast as possible.”

For power sensitive customers it is possible to do many optimizations

  • High Vt’s and standard cells can be selected for minimum power; performance will be less as well, but leakage power will be minimized and performance/watt will be maximized
  • We can offer several options for enabling very low power modes (off/sleep/deep sleep) while retaining state to return quickly to full speed operation
  • It is also possible to offer body back bias for even further power optimizations

We have implemented several different power optimized eFPGA implementations for customers already.

High reliability eFPGA

eFPGA, like FPGA chips, use bitcells to program the array and flip flops to hold state.

Both are susceptible to soft errors, just like microprocessors and ASICs. These errors are infrequent and most customers ignore them.

But there are some applications where very high reliability is required, for example autonomous vehicle control systems, space applications and some medical applications.

Scrubbing is an option for increasing reliability which is possible with standard eFPGA. If this is not sufficient, there are two other options:

  • Bit cells and flip flops that are triply redundant: three storage elements are used with an XOR function so that if one is flipped the output is still correct (circuitry can also correct the odd-man-out storage element)
  • Rad Hard by Design storage elements, supplied by the customer, where circuit design techniques result in much more soft error resistance than foundry sponsored standard cells

Both of these approaches increase area, but if reliability is a must, they can be implemented. And we have done so for multiple customers.

eFPGA cost/area reduction

For very high volume applications there are options to consider to reduce the area of eFPGA.

Here are a few:

  • Architectural: the current EFLX tile is designed to work as a standalone eFPGA and in arrays of 8×8 or more to support large, complex designs requiring a very large numbers of LUTs (>250K LUTs). To do this means that we have to put a large amount of interconnect resources into the single EFLX tile which are not needed if the array is small. Suppose a customer only wants small arrays; then we can remove interconnect resources resulting in a smaller tile. This optimization will also require some changes in the EFLX Compiler. This increases design cost but is worth if it a customer plans significant volumes where every mm2 counts.
  • Metal stack: we use many fewer metal layers than traditional FPGA. This allows us to support most of the metal stacks offered by the foundry to capture the most number of customers. If a customer is already using lots of metal layers, we can re-layout the tile utilizing the extra metal layers and reducing the array taken of the EFLX tile.
  • Circuit: the existing EFLX tile is all standard cells and we meet logic design rules. Traditional FPGA is not designed this way: they have teams of 50+ engineers doing full custom circuit design. We can apply a similar approach to the parts of the EFLX array on a 80/20 strategy. Design cost and time goes up but area can be reduced.


eFPGA adoption is taking off. As customers plan dozens of chips on a node or very high volumes, the economics allow consideration of a range of optimizations to better shape the eFPGA to maximize their SoC’s value proposition.

Leave a Reply

(Note: This name will be displayed publicly)