Improving the overall RRAM test quality, enabling mass commercialization of RRAMs.
Abstract:
” Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes the RRAM device to intermittently change its switching mechanism from bipolar to complementary switching, resulting in undefined state faults. First, we characterize the IUSF by analyzing RRAM devices, and demonstrate that a single RRAM device can suffer from the IUSF up to 1.068 % of its switching cycles; we relate the IUSF to two defects: capping layer doping, and over-forming. This clearly shows the importance of detecting this fault. Second, we develop a device-aware defect model that accurately describes the physical behavior of these defects and gives essential insights into the IUSF’s behavior and its detection. Third, we perform fault modeling by applying the device-aware defect model, and the results are used to develop high-quality test solutions for the IUSF. The contributions in this work improve the overall RRAM test quality, which enables mass commercialization of RRAMs.”
Find the technical paper here.
M. Fieback, G. C. Medeiros, A. Gebregiorgis, H. Aziza, M. Taouil and S. Hamdioui, “Intermittent Undefined State Fault in RRAMs,” 2021 IEEE European Test Symposium (ETS), 2021, pp. 1-6, doi: 10.1109/ETS50041.2021.9465401.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Key pivot and innovation points in semiconductor manufacturing.
Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.
Thinner photoresist layers, line roughness, and stochastic defects add new problems for the angstrom generation of chips.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Less precision equals lower power, but standards are required to make this work.
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
How customization, complexity, and geopolitical tensions are upending the global status quo.
127 startups raise $2.6B; data center connectivity, quantum computing, and batteries draw big funding.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Ensuring that your product contains the best RISC-V processor core is not an easy decision, and current tools are not up to the task.
ITRI had discovered this years ago; it was not intermittent but could be reproduced under certain SET conditions. Likewise, the solution is also an appropriate operation, which can be found easily.