IP Design Essentials For Reliability And SoC Integration

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law.

Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single system on chip. As IP designers are busy chasing the moving target of an evolving PDK, they are forced to address greater reliability challenges. A systematic IP verification and validation methodology is required to ensure power noise integrity and reliability of IPs for a wide variety of SoC-based applications.

An earlier blog discussed how to ensure power integrity of such IPs. This blog will focus on the essentials of designing an IP for reliability before and after integration into an SoC.

EM Analysis
Current density typically increases by 25% from one technology node to another, while via EM margin reduces by 30%. The increased current density on smaller geometries lead to local heating, which in-turn exacerbates electromigration (EM) on wires and vias. Over-designing or under-designing can impact the ability to leverage the drive current benefits of advanced technology. Hence a design driven layout based analysis platform is required for EM analysis.

EM rules are becoming complex and continuously evolving from one PDK to another as the technology matures. IP design houses typically work with multiple foundries in parallel, with each foundry defining their own set of EM rules. The credibility of a reliable EM analysis methodology is governed by its ability to determine actual EM issues and eliminate false violations, since much of designer’s time can be wasted fixing EM issues that are not real. The essence of foundry certification — IR/EM sign-off analysis — is that the EM analysis is optimal, effective and can be relied upon.

Restrictive design rules, strong dependence between circuit and layout design, and greater power noise and reliability issues in advanced technology nodes are all increasing the challenges for IP designers to deliver quality IP in time. The lack of visibility into the applications that an IP will be used for is another challenge.

Configurability of an IP requires comprehensive power/signal EM coverage and sign-off using vectorless and vectored analyses. With standard cell EM check being mandated at advanced technology nodes, cell-level EM analysis for different combinations of frequencies and load conditions is gaining traction. A multi-cycle, multi-state-based analysis methodology, together with the ability to visually inspect layout issues using current and EM maps will help debug and fix EM violations sooner.

EM analysis is not a one-time sign-off process. It is an iterative process from early in the design flow, and is most effective when vectorless analysis is used to identify and fix EM violations as soon as layout data is available. Waiting until sign-off stage is too late and almost always leads to being late-to-market or poor quality.

Figure 1: Complete EM sign-off flow

Thermal Analysis
EM limit deteriorates with temperature. For finFET technology nodes, the thermal impact due to self-heat is significant, leading to EM issues on wires and vias. Using a blanket delta T value for computing EM limit leads to pessimistic analysis, making it difficult for a designer to fix real EM violations. A thermal analysis tool that can compute the actual thermal gradient on an IP and re-calculate EM limits on various wires is not only more effective in identifying and fixing EM violations, it is becoming mandatory for high performance and ultra-low power designs.

Figure 2: Thermal integrity coverage

ESD Analysis
With prominent use of IPs in high speed IOs and SoC peripherals, ESD verification is becoming critical and is now one of the sign-off criteria. Typical issues caused by ESD are device breakdown, interconnect meltdown and cross domain problems. ESD window is reducing with each new node and conventional approaches such as DRC checks are no longer sufficient for sign-off. What is needed is a simulation-based approach that can detect connectivity, resistance and current density from early in the design cycle to sign-off. With decreasing oxide thickness, ESD schemes used in one technology is not guaranteed to work in the next. ESD robustness per area varies a lot between foundries and different layout structures even for the same technology node. The increase in resistance, current densities, associated joule heating, as well as the use of ultra-thin gate oxides directly impact ESD robustness. Lack of snap back protection and degraded diode protection in sub 20nm process nodes are pushing the need for bigger ESD devices which impact placement. With ESD failures impacting first time silicon success, it is now a sign-off requirement for advanced nodes and a streamlined approach as shown in the figure 3 is necessary from early analysis to sign-off.

Figure 3: ESD integrity coverage

IP Integration: An IP is not only required to work stand alone, it should also work in the context of rest of the circuits including other third party IPs in a target SoC. IP integration and verification is regarded as one of the biggest challenges faced by SoC designers. Same IP operating in two different modes can see very different voltage drops at the top level. To ensure power integrity of an IP across levels of hierarchy in the SoC, the IP has to be accurately modeled and characterized for different modes of operation in top-level voltage drop analysis. Hand-off of the IP to a SoC team must include the electrical and physical properties of the IP along with any embedded constraints for power integrity sign-off. At the SoC-level, the onus is on the SoC designer to accurately model the switching scenarios corresponding to different modes of IP usage and verify power integrity and reliability.

ESD protection that works at the IP level may not work at the SoC level due to poor connectivity to other IPs and circuits in the SoC. Therefore, it is important to analyze the ESD protection schemes at the SoC level across multiple voltage domains to make sure that they provide the intended low resistance path to discharge a potential ESD event without stressing the functional devices.

Figure 4: IP integration validation at SoC level using model roll up

Using a design, analysis and verification methodology to ensure power integrity and reliability such as EM and ESD of an IP at the SoC-level application is mandatory for IPs designed for advanced process nodes.