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Leveraging Multi-Protocol PHY For PCIe To Cope With SoC Design Complexity

How a refined and enhanced PCIe multi-protocol PHY IP block can pave the way to a new approach in SoC architecture and planning.

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Now in the post-Moore’s Law era, the fast-evolving semiconductor market is continually geared toward higher performance and feature-rich integrated chip (IC) solutions. More functional design blocks integrated with growing interconnections—to not only increase the overall throughput but also expand the I/O connectivity—resulted in a more powerful system on chip (SoC). This increasing complexity further challenges SoC development tradeoff among the feature; the performance, power consumption, and area (PPA); and the time to market (TTM).

PCI Express (PCIe) has been widely adopted as the primary I/O interconnect since its first debut in 2003 (PCIe 1.0 standard release) in wide breach of applications, from hyperscale, artificial intelligence / machine learning (AI/ML), and aero/defense, to 5G communications, mobile/consumer, automotive, etc. It’s a versatile, high-performance, robust, and mature interconnect standard with full backward compatibility, which enables a solid and strong ecosystem in the industry. This paper discusses how a refined and enhanced PCIe multi-protocol PHY IP block can pave the way to a new approach in SoC architecture and planning with the benefits of shortened TTM and competitive development cost.

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