Looking Beyond Moore’s Law

There is a change taking place in chip scaling. There are now two chip-scaling paths–aggressive and cost sensitive. What does it all mean?


For decades, chip scaling has followed a simple linear curve. In this curve, the transistor gate-pitch scales at 0.7x every two years. This is the driving force behind Moore’s Law, which states that the number of transistors per chip roughly doubles every two years.

But starting at the 16nm/14nm node, there is a change taking place in chip scaling. According to a chart from Imec, there are now two separate chip-scaling paths in the industry —aggressive and cost-sensitive.

Intel is maintaining the status quo and pushing the aggressive scaling curve. In contrast, the silicon foundries are following the cost-sensitive path, which, in some respects, is upsetting the apple cart and defying Moore’s Law.

Simply put, traditional scaling is slightly slowing down at the foundries. The big question is clear: Will the slight slowdown in scaling at the foundries impact OEMs and consumers? Answer: In the near term, no.

Long term, however, the industry could see a fundamental shift, in which the nodes will extend beyond the two-year or so cadence. Perhaps a three- to five-year cadence makes more sense at 10nm and beyond. And in some respects, extending the nodes could be a healthy development for the industry, rather than a detriment.

Two paths

For years, the foundries were (and still are) behind Intel in process technology, but they all followed the same technology roadmap and specs. There were some deviations, however. The foundries were ahead of Intel in terms of bringing up 193nm immersion lithography into mass production. Intel was the industry’s first chipmaker to adopt high-k/metal-gate. And, of course, Intel was the first vendor to jump on finFETs.

Meanwhile, in the broader process technology arena, there will be a major but subtle change at the 16nm/14nm node. For example, at Intel, the interconnect pitch is 64nm at the 14nm node. In contrast, at the same node, the interconnect pitch is 80nm at the foundries.

In fact, Intel has made a big deal about the disparity, claiming the company has a huge advantage over the foundries in terms of area scaling.  The foundries have dismissed those claims.

At present, though, it is a moot point. The feature size specs between the two camps–aggressive and cost-sensitive–are not that far apart. As before, what really matters is the functionality and the cost of a given chip.

What also matters is whether the chip-scaling curve will continue to go down the traditional linear path. Or, will it resemble a staircase? This is where the nodes are introduced and then extended for a long period.

Time will tell, but the signs point towards the same trend. There is a “slowing of scaling to smaller feature dimensions,” said Handel Jones, chief executive at International Business Strategies. “Key reason for slowing is difficulty in reducing (the) cost-per-gate and cost-per-bit.”

In one prediction, Jones said there is a 90% chance that the 10nm node gets delayed. “10nm will likely be postponed,” he said. “Cost-per-gate will be prohibitive and unclear as to demand other than high-speed processors and FPGAs.”

At one time, leading-edge chipmakers would shudder over a possible node delay. Now, a slowdown in scaling, or a node delay, would not exactly be the end of the world. It would give chipmakers and OEMs a chance to recoup their investments.

Today, in fact, smartphone customers aren’t exactly screaming for 10nm processors. There are other issues on the table. For example, smartphone makers have or will incorporate 64-bit application processors in their new systems. But for the foreseeable future, the operating systems and software apps will still need to play catch up with the advances in hardware.

The world is still moving from 3G to 4G wireless networks. Over time, the industry will see faster 5G networks. This, in turn, will require new breakthroughs in the radio-frequency (RF) front-end. For example, there is still room for improvement in multi-mode, multi-band power amps to support the growing number of 4G networks.

Better and higher-resolution screens are also required in today’s devices. And, of course, the biggest issue for today’s mobile devices is fairly clear—lackluster battery life.

So let’s not stop Moore’s Law. Instead, let’s take a step back and innovate where it’s needed. And let’s look beyond Moore’s Law and perhaps regain our senses in the process.

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  • Bill Martin


    Your article discusses two silicon options to continue Moore’s Law. Many can debate if Moore’s Law will continue and how it should be applied. I view Moore’s Law as a ‘system density’ principle that expands beyond just linear shrinking silicon nodes. Silicon shrinking led to performance performance/density improvements and costs savings for the last 30+ years. Around the 1u (yes micron) time frame, gate delays were the prime impediment to faster silicon. After 1u, the focus shifted to interconnect delays as the key to faster silicon. As you mention in the above article, additional silicon shrinks are becoming very costly and the cost per transistor is hitting an inflection point where each gate is more expensive than previous silicon nodes.

    The ‘old world’ (jumping to the latest silicon node) is no longer a ‘no brainer’ economic decision. But is another side of this solution, packaging, that can offer significant options with 2.5 and 3D packaging solutions (silicon, glass or other interposers). These interposer solutions can dramatically shorten interconnect delays as well as power, area, weight, etc allowing users to mix and match proven, cost efficient silicon that is optimized for the functionality/performance required (i.e. heterogeneous silicon ICs). Silicon solutions can use the lowest cost, best matched product (35u, 180nm, 90nm, 45nm, etc) for specific portions of their system design.

    Many focus on the full 3D solution (stacking die) as ideal and over time it will be. But today, 2.5D can offer significant re-use of older silicon technologies on the next generation PCB platform (interposers) using bump or wire bond . The old world, 2 dimensional cost analysis, will be replaced by new 3 dimensional cost analysis where significant improvements can be achieved using a mix of old (silicon) and new (packaging) technologies.