Low-Power And RF Design Heighten Signal-Integrity Concerns

By Ellen Konieczny

As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all.

For low-power and radio-frequency (RF) designs, which are being produced at a steady climb, this challenge is even more daunting. Such designs involve numerous aspects that make it more difficult to ensure signal integrity. Due to their very nature, RF designs also face more severe consequences if signal-integrity rears its head in the form of problems like interference and noise.

Among the design aspects that threaten low-power designs, for example, are multiple power operating modes, multiple voltage supplies, voltage and frequency scaling, and voltage islands. As noted by Shekhar Kapoor, Synopsys’ senior product marketing manager for the Galaxy Signoff Solution, “The use of low-power techniques, such as power islands and on-off switching behavior, can exacerbate signal-integrity issues. The potential issues to worry about include dynamic voltage drop, power-grid electromigration, and electromagnetic-interference (EMI) noise. All these effects could worsen if care is not taken to manage the in-rush current in turning on power switches, for example.”

To overcome this challenge, Kapoor recommends a holistic approach to handling signal integrity that has in-design and signoff analysis working together. To mitigate the signal and power-grid integrity issues, place-and-route tools must provide various optimization and fixing techniques. Examples include wire-width adjustments, multiple via insertions, and buffering. In addition, the signoff parasitic extraction and timing/signal-integrity solutions must offer detailed debug and fixing to address any undetected problems before tapeout. At smaller nodes—especially below 40-nm process technologies—the parasitics have become context-specific (i.e., layout-dependent). To ensure silicon accuracy, the extraction tools must model the context-specific device parasitics as part of the extraction process. They can then account for the amplified effects of the MOS device parasitics at smaller nodes.

Beyond a winning approach, the key to successful low-power design is really a mindset. The techniques used to achieve low-power design introduce a high level of complexity at the levels of system design, functional verification, IC physical design, and IC testing. To achieve success, it is therefore essential that the designer keep the low-power aspect in mind beginning with the earliest stages of design. According to Michael Buehler-Garcia, director of marketing at Mentor Graphics’ Design to Silicon Division, “Engineers need ways to evaluate different architectural approaches to power reduction early in the design process, at the system level. They also need to verify functionality in detail, ensuring that transitions between power modes do not create logical errors and that state retention is handled correctly when parts of a chip are temporarily powered down.”

RF Design Poses Further Hazards
The RF aspect of a design adds a much more complex set of challenges, as it is essential that the integrity of the communication path be maintained. Among the chief concerns are electromagnetic (EM) degradation and EM-interference (EMI) noise. Dave Robertson, vice president of analog technology for Analog Devices, says his company sees the maintenance of signal integrity being comprised of two elements: Amplifying, processing, and transmitting the signal with minimal degradation due to distortion or device noise, and minimizing the effects of induced external signals from crosstalk, power-supply noise, or other external interference

The simplicity with which those two goals can be stated belies their complexity—especially considering the short time to market for RF products. This issue is compounded by the fact that signal integrity traditionally has been a concern in the digital-circuit rather than the RF domain. Thankfully, as signal-integrity issues began to rear their heads in high-speed communications designs, software developers have pruned signal-integrity analysis environments to address both device and circuit models. With today’s shrinking ICs interacting more with both active neighboring devices and interconnects, it is crucial that such interactions are modeled accurately.

During analog design, custom IC layout and simulation tools are used to accurately model the behavior of an RF or other analog circuit. The designer can therefore determine if signal integrity will be compromised by interactions within the cell itself. Yet Mentor’s Buehler-Garcia notes the designer also must avoid signal-integrity problems when the RF cell is placed within the context of a full mixed-signal IC, which may interact with other circuits including digital signals.

Once active and passive device models have explored all of the high-frequency effects, signal integrity may be ensured by using a comprehensive set of analysis engines that leverage that modeling capability. According to Ted Mido, senior staff engineer for Synopsys’ circuit simulation product line, designers must be sure to exercise both of these options. He notes that most designers rely on time-domain analysis for final behavioral verification. Therefore, the baseline would be to have high-performance, high-capacity transient and transient noise analyses.

In the early design phase, Mido notes that system or subsystem behaviors may be predicted by using small-signal frequency-domain analysis to predict system S-parameters, small-signal noise parameters, transfer functions, and so on at a particular operating point. In addition, a statistical eye-diagram simulation can predict deterministic channel noises like inter-symbol interference, duty cycle distortion, and periodic noise. Finally, large-signal steady state analysis may be used to predict nonlinear and modulation effects. Of course, these analysis engines must be able to accurately accommodate all of the high-frequency effects originally modeled.

Although electronic-design-automation (EDA) tools are clearly working to ensure signal integrity in RF designs, a lot may be gained in the hardware design as well. As ADI’s Robertson notes, “There are CAD tools for capturing and analyzing parasitic resistance and capacitances, but it can be difficult to come up with models of sufficient accuracy, and for large chips it is generally impractical to exhaustively capture and simulate these parasitics. Different circuit topologies and architectures may make the problem much better or much worse, so circuit innovation can often relieve what was perceived as a ‘hard physical constraint.’”

Beyond Moore’s Law, ADI recognizes a number of challenges spawned by the functional density involved in mixed-signal and RF integration. Although active power density is a fundamental challenge, some relief may be found in advanced packaging solutions. Similarly, powering down idle blocks offers advantages when dealing with inactive power density from leakage currents in very deep-submicron CMOS. It should be noted that this benefit does come at the cost of more sophisticated power management circuits and systems.

In terms of current density, the fine metal pitch and increasing functional densities can cause electromigration and IR drop problems in the on-chip interconnect. The process solution is to use copper and thick copper interconnect. Yet bump and flip-chip packaging can provide a 2D bonding approach so these currents do not need to be routed all the way across the chip. Such approaches also reduce the inductance of these connections.

The signal-integrity puzzle will only grow more complex as designs continue to shrink while consuming less power and incorporating more wireless capability. Going forward, for example, it is critical for designers to realize that signal integrity will need to be considered between chips as well as on chips. Mido states, “The massive integration of cores on vertically stacked chips (3D ICs) that don’t necessarily feature the latest transistor technology node is becoming common. Therefore, high-speed communication between cores/chips is becoming important. With the increasing operational frequencies of these digital communication bus/links, bit-error-rate (BER) prediction is also becoming important (See Figure 1).”

Figure 1: For accurate bit-error rate predictions in high-speed digital communications, it is critical to account for aspects like high-frequency loss mechanisms, millions of possible bit patterns, special techniques for equalizing digital signal shape both in transmitter and receiver side, and multiple noise mechanisms.