LP Test Strategies

Best practices in testing to avoid a smoking chip, maximize yield, and still keep costs under control.


By Luke Lang
Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how to deal with the problem.

When a chip burns up on the tester, it is very clear that test power needs to be reduced drastically. We are not talking about 10% to 20% reduction. We are talking about 50+% reduction. One way to achieve this kind of power reduction is to decrease the tester clock frequency. However, this has a very undesirable consequence. It increases the cost of test. A 50% reduction in test clock frequency means doubling the test cost. This is clearly not a viable solution.

Another method is to test only a portion of the chip at a time. Let’s say a chip contains 10 major blocks. If we were to test 2 blocks at a time, then we would achieve 80% reduction in dynamic power. In the early days, designers implemented this kind of test power reduction by gating off selected clocks during test mode. In recent years, leakage power has become significant and is not addressed by clock gating. A much more effective method to reduce test power is to take advantage of the fact that some of these blocks can be shut off. Shutting off some blocks while testing the remaining blocks eliminates both dynamic and leakage power. The entire chip can be tested by rotating the on/off blocks until sufficient test coverage is achieved.

To implement this, the tester must have direct control of the power switch enable signals. Also, the scan chains must be designed with power shutoff in mind. Using the above example, we would need one set of scan chains for each pair of blocks. This may not be practical because we could exceed the tester pin count. Another alternative is to have one set of scan chains for all blocks and design capabilities to bypass the blocks that are turned off. Conceptually this is not difficult work, but it is tedious and error-prone. It is best to use a DFT tool that can automate this function.

Once again, this is where the power intent file is extremely useful. It contains all of the power switch and isolation control signals. Test mode logic can be automatically generated and inserted into the netlist to allow direct access to these key LP control signals by the tester.

Controlling total test power will ensure that a chip does not burn up on the tester, but it will not ensure successful testing. There are other power issues that could negatively impact yield. We will discuss them next month.

PS: With knowledge of the power switch and state retention control signals, a DFT tool also can generate test patterns for state retention registers. This involves scanning in a known pattern, saving the retention register contents, switching off and then on the power domain, restoring the retention registers, and then scanning out the register content for comparison. While this is not related to test power reduction, it does illustrate another use of the power intent file by a DFT tool.

—Luke Lang is engineering director at Cadence.

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