Manufacturing Bits: Dec. 31

Bringing Graphene Down To Earth
For years, the semiconductor industry has been looking at graphene as a next-generation technology for a multitude of applications. One potential application, the graphene field-effect transistor (GFET), has been developed by various companies and universities.

There are several advantages and disadvantages with GFETs. On one hand, GFETs have a higher mobility and a saturation velocity much larger than any semiconductor, according to Andrea Ferrari, a professor at Cambridge University and director of the Cambridge Graphene Centre. “Being only one atom thick, graphene has a potential to overcome state-of-the-art silicon and III-V semiconductors in high-frequency transistors at the ultimate scaling limits,” Ferrari said.

The problem with graphene is widely known, however. “There is no bandgap,” he said during a keynote presentation at the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C. “The absence of a bandgap is a major hurdle in the development of realistic circuits, since this gives a non-zero off state drain current, which leads to considerable static power dissipation.”

There have been several efforts to devise GFETs with bandgap-like properties. But until there is a viable solution to the problem, it’s unclear if or when graphene, or the GFET, will become mainstream technology. “Graphene could potentially complement (semiconductor technology), but not supplant it,” he said. “What’s the killer application for graphene? We still don’t know.”

Still, there are several emerging applications for graphene. “An important example of such circuits is ring oscillators integrated on CVD graphene,” he said. “They oscillate at frequencies above 1-GHz in air, and can be used in a wide range of applications in digital and analog electronics, when ultra-fast operation is favored over static power dissipation. The oscillation frequency could be increased through further advances.”

In another recent effort in the lab, Cambridge and others have devised bilayer GFETs, which operate as Terahertz-based broadband photodetectors. The technology is promising in various applications, such as medical, homeland security and environmental monitoring.

The GFETs are based on plasma-wave excitation. Researchers developed devices in the 0.29 to 0.38 THz range and within the photovoltage and photocurrent mode. This is achieved by using either 1μm gate lengths or buried gate geometries on a bilayer graphene.

In the manufacturing process, flakes are exfoliated from graphite. They are placed on a silicon substrate covered with silicon dioxide. Then, two sets of FETs are fabricated. The source and drain are patterned using direct-write e-beam lithography, according to researchers. Using atomic layer deposition (ALD), hafnium-oxide is deposited. This, in turn, creates electrodes for the source and drain.

New Spin On Graphene
Graphene behaves like a typical conductor. But apply a magnetic field perpendicular to graphene and the current flows in one direction. The direction could be clockwise or counterclockwise, a phenomenon known as the quantum Hall effect.

The Massachusetts Institute of Technology (MIT) has put a new spin on graphene. Under a magnetic field at low temperatures, MIT found that graphene can filter electrons according to the direction of their spin. Researchers from MIT applied a second magnetic field to graphene. As a result, electrons can move around the conducting edge in either direction.

Recently, a new method has emerged with the recognition that symmetry-protected topological (SPT) phases can host robust surface states, according to researchers. With this concept in mind, MIT demonstrated that charge-neutral monolayer graphene has a quantum spin Hall state.

This effect takes place when the device is subjected to a large magnetic field with respect to the graphene plane. Researchers also observed transport signatures of gapped edge states. This represents a new electronic system with a tunable bandgap and an associated spin texture. “We created an unusual kind of conductor along the edge,” said Andrea Young, a Pappalardo Postdoctoral Fellow in MIT’s physics department, on the university’s Web site. “We can turn these edge states on and off.”

So, in effect, “we can make circuits and transistors out of these,” Young said.

On a piece of graphene (the horizontal surface with a hexagonal pattern of carbon atoms), in a strong magnetic field, electrons can move only along the edges, and are blocked from moving in the interior. In addition, only electrons with one direction of spin can move in only one direction along the edges (indicated by the blue arrows), while electrons with the opposite spin are blocked (as shown by the red arrows). Photo courtesy of MIT.

Monolithic 3D Carbon Nanotubes
At the recent IEDM, Stanford University presented a paper that described a process for developing monolithic 3D chips using carbon nanotube field-effect transistors (CNFETs).

The subject of monolithic 3D chips is generating some momentum. Monolithic integration involves a process of stacking, aligning and connecting leading-edge transistors on top of each other to form a monolithic 3D chip. Using standard vias, monolithic 3D ICs are said to provide 10,000 times more connections at smaller feature sizes than stacked 2.5D/3D TSV technology.

Instead of transistors, Stanford is stacking CNFETs. Researchers demonstrated three layers of CNFETs, which are connected using conventional vias. “We also demonstrate that such monolithic 3D logic gates can operate correctly over a range of supply voltages from 3V to 0.2V,” according to Stanford’s paper at IEDM. “For monolithic 3D integration of CNFET digital systems, one must overcome the challenges of mispositioned CNTs and metallic CNTs.”

To overcome these challenges, Stanford has devised a new fabrication technique, dubbed the 3D-VLSI m-CNT Removal (3D-VMR). “Our new 3D-VMR technique uses local back-gates (LBGs) on each layer to maintain strong gate control for effective m-CNT electrical breakdown on each layer of a monolithic 3D IC,” according to the paper.

“Oxide layers are deposited through atomic layer deposition (ALD) process as LBG gate dielectric so that LBGs can serve as effective gates for CNFETs in the final design,” according to the paper. Then, the source/drain electrodes are patterned at minimum metal pitch to form structures on each layer of a monolithic 3D IC.