Manufacturing Bits: June 17

PiezoFET debuts
The University of Twente MESA+ Research Institute and SolMateS have put a new twist on the finFET. A piezoelectric stressor layer has been deposited around the finFET, thereby enabling what researchers call the PiezoFET.

The PiezoFET could enable steep sub-threshold slope devices. In the lab, this device was also able to reduce the leakage by a factor of five.

The transistor current flows through tiny silicon bars, which are enveloped by a package of conductor layers and piezo-electric material. The conductors control the amount of mechanical tension, and also the quantity of electrons in the silicon. In this way, the power can be turned on and off. (Source: University of Twente)

In the lab, researchers devised the PiezoFET. It consists of the following materials stack–a piezoelectric stressor layer; lead–zirconate–titanate (PZT); and aluminum–nitride (AlN) deposited on n-type silicon FinFETs.

When applying a voltage to the PiezoFET, the piezoelectric material expands. It also compresses the silicon in the transistor with a pressure of about 10,000 atmospheres, which enables the electrons to flow through the device much faster. The strain was partly formed by the bias over the piezoelectric layer. This, in turn, “indicates the converse piezoelectric effect related tunable strain in both the silicon channel and gate oxide,” according to researchers.

For the PZT, a piezoelectric response in the range of 100 pm/V was obtained by researchers. But the piezoelectric response for the AlN device was 13 pm/V, which was far less than expected. Still, with the PZT stressor, a 20% to 50% change in the mobility and a change in the sub-threshold slope have been observed. In fact, the device demonstrated a sub-threshold slope of about 5 mV/decade.

“The design is still fairly crude where the material is concerned. With the further development of the transistor, it should therefore be possible to achieve a further significant increase in efficiency,” said Ray Hueting, a processor from the University of Twente, on the university’s Web site.

Graphene-like 3D materials
Graphene is a honeycomb lattice made of carbon. The 2D material is strong and conducts electricity, but graphene also lacks a bandgap. This has prevented graphene from becoming a mainstream technology for semiconductor devices.

The University of Oxford, SLAC, Stanford and Lawrence Berkeley National Laboratory have advanced the study of a new material. The material, cadmium arsenide, has the same properties as graphene, but it comes in a 3D form.

Oxford, SLAC, Stanford and Berkeley Lab have discovered that a sturdy 3D material, cadmium arsenide, mimics the electronic behavior of 2D graphene. (Source: SLAC)

Compared to graphene, cadmium arsenide could be easier to craft into practical semiconductor-like devices. This class of materials are called 3D topological Dirac semimetals (TDSs). “In contrast to graphene, the Dirac points of such a semimetal are not gapped by the spin-orbit interaction and the crossing of the linear dispersions is protected by crystal symmetry,” according to a recent paper from Princeton University and IFW Dresden. “In combination with broken time-reversal or inversion symmetries, 3D Dirac points may result in a variety of topologically non-trivial phases with unique physical properties.”

On SLAC’s Web site, Yulin Chen of the University of Oxford, said: “Now more and more people realize the potential in the science and technology of this particular material. This growing interest will promote rapid progress in the field–including the exploration of its use in functional devices and the search for similar materials.

“We think this family of materials can be a good candidate for everyday use,” Chen said, “and we’re working with theorists to see if there are even better materials out there. In addition, we can use them as a platform to create and explore even more exotic states of matter; when you open a door, you find there are many other doors behind it.”

Nanotube bumps for packaging
Auburn University has developed a fabrication process that will enable carbon nanotube bump interconnects for chip-packaging applications. The proposed process is capable of fabricating carbon nanotube bumps at room temperature with high resolution and adjustable bump heights.

In today’s chip packaging, flip-chip is the mainstream technology. Flip-chip also uses solder bumps, which are susceptible to electromigration in the micro-scale regime, according to researchers.

In the distant future, carbon nanotube bumps could replace flip-chip. Carbon nanotubes have good electrical properties and high electromigration resistance. Carbon nanotubes “can be flexible and stress decoupled, which is beneficial to accommodate for coefficient of thermal expansion (CTE) mismatch,” according to researchers.

Most of the research on carbon nanotube interconnects makes use of processes based on chemical vapor deposition (CVD). But, according to researchers, CVD requires process temperatures greater than 700 °C. This is not compatible with conventional packaging.

Auburn has devised a process that can be performed at room temperature, making it compatible with packaging processes. One way to achieve this is to use a surfactant, which is used to disperse and stabilize a carbon nanotube into a solvent. Dispersion is essential for depositing a uniform film of carbon nanotube bumps. Sodium dodecyl sulfate (SDS) is the surfactant used in dispersing carbon tubes.

Researchers used SDS from Sigma-Aldrich and CG-200 carbon nanotubes from Southwest Nanotechnology. CG-200 was chosen due to its high percentage of single-wall nanotubes (SWNT).

“SDS were added into DI water and stirred for 10 min. before adding CNT to ensure complete dissolution. Next, CNTs were added to the solution and stirred for another 10 min.,” according to the research paper from Auburn. “Ultrasonication was used to further disperse the quasi-dispersion using a tip sonicator (Misonix XL2020–power: 550 W, frequency: 20 kHz) with an amplitude of 40% for 60 min.

“To avoid overheating of the dispersion, the ultrasonication process was paused for 2 (seconds) after every 5 (seconds) of sonication and the dispersion was kept in an ice bath during the process. Sequentially, a 30 minute, 3000 rpm centrifugation step was used to separate aggregates and precipitates from the dispersion,” according to the paper.

“The supernate was carefully decanted and stored at 10°C until the next step to minimize aggregation. Before centrifugation, the dispersion contains 0.2 wt% SWNT and 0.4 wt% SDS. After centrifugation, the concentration of materials in water is marginally reduced because the SWNT and surfactant are well-dispersed and minimally removed,” according to the paper.