Manufacturing Bits: May 16

Musical learning chips
Imec has demonstrated a neuromorphic chip. The brain-inspired chip, based on OxRAM technology, has the capability of self-learning and has been demonstrated to have the ability to compose music.

Imec has combined state-of-the-art hardware and software to design chips that feature these characteristics of a self-learning system. Imec’s goal is to design the process technology and building blocks to make artificial intelligence to be energy efficient so that that it can be integrated into sensors.

Facebook, Google and others have developed systems using machine learning, based on traditional graphics processor units (GPUs). Basically, these systems use neural networks. In a neural network, the system crunches the data and identifies patterns. Over time, it learns which of those attributes are important.

In contrast, neuromorphic computing uses specialized hardware to enable machine learning. In simple terms, neuromorphic chips are fast pattern-matching engines that process the data in the memory. In theory, these chips promise to enable systems that can perform several tasks, such as computer vision, data analytics and machine learning. The ultimate goal is to realize true artificial intelligence (AI).

Meanwhile, it is Imec’s goal to further advance both hardware and software to achieve very low-power, high-performance, low-cost and highly miniaturized neuromorphic chips that can be applied in many domains ranging for personal health, energy and traffic management. For example, neuromorphic chips integrated into sensors for health monitoring would enable to identify a particular heartrate change that could lead to heart abnormalities, and would learn to recognize slightly different ECG patterns that vary between individuals. Such neuromorphic chips would thus enable more customized and patient-centric monitoring.

“Because we have hardware, system design and software expertise under one roof, Imec is ideally positioned to drive neuromorphic computing forward,” says Praveen Raghavan, distinguished member of the technical Staff at Imec. “Our chip has evolved from co-optimizing logic, memory, algorithms and system in a holistic way. This way, we succeeded in developing the building blocks for such a self-learning system.”

Separately, Imec and Holst Centre announced the development of a sensing technology to detect eye movement in real time based on electrical sensing. Paving the way for the next generation of eye-tracking technology, Imec’s solution has promising applications in the fields of virtual and augmented reality.

Imec’s sensors were integrated into a set of glasses, with four built-in electrodes around each lens, two to pick up the eye’s vertical movement and two for horizontal movements. Parallel to that, an advanced algorithm was developed to translate the signals into a concrete position, based on the angle the eye is making with its central point of vision. Imec’s solution also offers insights on the eye’s behavior, like the speed of movement or the frequency and duration of blinks.

Nanocar races
A team of Rice University and the University of Graz finished first in the inaugural “Nanocar Race.”

The recent event, conducted in Toulouse, France, involved a race of molecular nanostructures from various teams across a 150nm course. The course track was constructed within a scanning electron microscope. The purpose of the race was to see how single molecules interact with surfaces.

The team of Rice and Graz deployed a two-wheeled, single-molecule vehicle with adamantane tires. The structure achieved an average speed of 95nm per hour. The average speed ranged from more than 300nm to less than 1nm per hour, depending upon the location along the course. The Swiss Nano Dragster team finished next, five hours later.

The Dipolar Racer designed at Rice (Source: Rice University)

The Toulouse course could only accommodate four cars. So the teams of Ohio University and Rice-Graz ran their vehicles on their home tracks and operated them remotely from the Toulouse headquarters. Five cars were driven across gold surfaces in a vacuum, but the Rice-Graz team used a silver track at Graz. The nanocar on the gold track was too fast to image. So Rice-Graz used a slower silver track.

The silver track under the microscope. Two Rice nanocars are in the blue circle at top. The lower car was the first to run the race, finishing in a 1½ hours. The top car was put through the course later, finishing in 2 hours. (Source: Rice University)

“This is the beginning of our ability to demonstrate nanoscale manipulation with control around obstacles and speed and will pave the way for much faster paces and eventually for carrying cargo and doing bottom-up assembly,” said Rice University chemist James Tour.

VLSI papers
At the upcoming 2017 Symposia on VLSI Technology & Circuits, Intel will present a paper on a 2.5D/3D digitally-controlled, integrated voltage regulator–based on a 14nm finFET process. The device also stacks an on-die solenoid inductor using through-silicon vias (TSVs) with a backside planar magnetic core.

“The target application is TSV-based 3D stacked heterogeneous multi-die packages, where stringent thermal constraints necessitate local VRs in each of the dies to operate at high power conversion efficiency in the light load regime and TSV-friendly area-efficient inductor integration is desired,” according to the paper.

Intel built an on-die solenoid inductor that uses 4.5 TSV-based vertical turns around the die along with a high-permeability planar magnetic core on the backside. “The inductance density is improved to 111nH/mm2, which is >2X better than conventional inductors with non-planar magnetic cores, and >8X better than planar spiral inductors. The regulator generates a 0.4V-1.1V output from a 1.2V input and high- power conversion efficiency (77%) for light load condition (1.5mA) is achieved through the use of hysteretic and pulse frequency modulation control,” according to Intel.

At the event, TSMC will present a paper on its next-generation CoWoS technology, enabling 2.5D/3D devices with high-bandwidth memory (HBM). “TSMC developed a CoWoS-2 WLSiP technology that integrated a VLSI SoC up to six 8-high HBM2 with suppressed warpage resulting in high package yield,” according to an abstract from the paper. “An ultra-large silicon interposer up to 1200mm2 made by a two-mask stitching process was used to form the basis of the CoWoS-2.”

IEDM
The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held in San Francisco from Dec. 2-6, 2017, has issued a call for papers seeking the best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Aug. 2, 2017. For the second year in a row the IEDM submission deadline is about 1½ months later than what had been the norm, reducing the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Authors are asked to submit four-page camera-ready abstracts (instead of the traditional three pages), which will be published as-is in the proceedings.

For more information, interested persons should visit the IEDM 2017 home page here.