Manufacturing Bits: Oct. 14

Toyota’s power steering IC
Today’s cars are making use of more electronics. The increase in electronic content is driving the need for high temperature and high voltage chips.

The electric power steering (EPS) system is one example. EPS provides power assist even when the engine is stopped. It also improves fuel economy compared to hydraulic power steering, according to automotive giant Toyota.

In automobiles, the EPS is handled by an electric control unit (ECU). It consists of a boost converter and a three-phase inverter to drive a three-phase brushless motor, according to Toyota. A switching power supply controller, which produces a gate drive voltage, is also required.

Toyota itself has developed a driver IC for EPS applications. The ASIC has been fabricated using an in-house SOI-BCD process, which can operate at the maximum voltage of 80V and at temperature from -40°C to 175°C.

The ASIC drives both the high- and low-side devices in the power-module. “The ASIC for the EPS application is integrated (in) the gate drivers of a boost converter and (a) three-phase inverter,” according to Toyota. “Each phase has a power terminal and GND terminal. The chip size of the ASIC is 3.8mm × 3.6mm.”

Silicon-on-nothing finFETs
IBM, STMicroelectronics and GlobalFoundries have developed several manufacturing techniques to enable a dielectric isolated (DI) finFET.

A DI finFET is basically a silicon-on-insulator (SOI) finFET. Two technologies—including a bottom oxidation through STI (BOTS) and a silicon-on-nothing (SON) process—can be used to fabricate DI finFETs. DI finFETs are also made on inexpensive bulk substrates, as opposed to a silicon-on-insulator (SOI) substrate.

“Dielectric Isolated (DI) finFETs exhibit superior electrostatic control compared to bulk finFET without needing heavy sub-fin punch-through stop doping, which increases device variability,” according to a recent paper from the three companies.

In the BOTS process, a silicon fin is first formed on a bulk substrate. This is done using local oxide isolation, which partly fills the gaps between the fins. Then, a thin capping nitride is deposited on the sides of the fin and above the hard mask.

“After opening the thin nitride layer on horizontal surfaces with an anisotropic etch, local oxide isolation is removed and the exposed silicon is pulled-back laterally with an isotropic etch,” according to the paper. “Gaps between fins are filled with oxide–an important step for mechanical stability. The bottom of the fins are oxidized from two sides until the active fin is isolated from the substrate. Capping nitride and part of the oxide are removed, leaving the fin standing on oxide.”

Meanwhile, in the alternative SON finFET process, a fin is formed by etching a tri-layer Si/SiGe/Si stack instead of plain silicon. “Subsequently the gate and the spacers are formed, mechanically anchoring the fin. Selective etching with HCl removes only the SiGe but not the silicon, creating a tunnel between the active fin and the substrate. Finally, the tunnel is filled with dielectric material such as oxide. The final fin is electrically isolated from the substrate,” according to the paper.

Nanowire FETs
Nanowire transistors are one of the futuristic candidates in the next-generation transistor race. In some respects, nanowire transistors are 3D-like devices, in which the nanowires are stacked on top of each other.

Previously, CEA-Leti and others have demonstrated a uniaxially-strained, Ω-gate nanowire transistor. Using a strain silicon-on-insulator (sSOI) process for the NFET, researchers developed a device with 10nm gate lengths.

In its latest work, CEA-Leti, along with STMicroelectronics and Soitec, have advanced the technology. Researchers have developed an Ω-gate nanowire PFETs on a compressively-strained–SiGe-on-insulator (cSGOI) substrate. Using germanium (GE) enrichment techniques, researchers developed devices down to 15nm.

In the flow, the cSGOI process starts with the epitaxy of a 12nm silicon-germanium (SiGe) film on a 300mm blanket SOI wafer. Then, the device undergoes the channel formation process, followed in order by active patterning, gate stack (high-k/metal-gate), spacer one formation, in-situ boron doping of the raised source/drain, implant, anneal, and a compressively-strained step.

The cSGOI substrates are fabricated with a Ge content of 20%, according to researchers. The SiGe thickness under the HfSiON/TiN gate is 11.5nm. “The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at LG=15nm,” according to the paper. “SGOI nanowires based on a Ge enrichment technique show high-performance (ION=860μA/μm at IOFF=14nA/μm) with excellent electrostatics (DIBL=110mV/V).”