Everything You Need to Know about FDSOI Technology


Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more di... » read more

FD-SOI: How Body Bias Creates Unique Differentiation


Fully depleted silicon-on-insulator (FD-SOI) relies on a very unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance in terms of power, performance, area and cost tradeoffs (PPAC), making it possible to cover from low-power to high-performance digital applications with a single technology platform. FD-SOI delivers numerous un... » read more

Ultra-Low-Power SAR ADC in 22 nm FD-SOI Technology Using Body-Biasing


Today’s sensor applications show a rising demand on miniaturized autonomous sensors nodes with extreme requirements on power dissipation. One core functionality of these sensor nodes is the conversion of analog sensor signals to digital data for post processing and data communication. In this work a 11-bit Successive Approximation Register (SAR) ADC with minimized power dissipation is develop... » read more

5 Issues Under The Foundry Radar


In the foundry business, the leading-edge segment grabs most, if not all, of the headlines. Foundry vendors, of course, are ramping up 16nm/14nm finFET processes, with 10nm and 7nm in R&D. The leading-edge foundry business is sizable, but it’s not the only thing going on in the competitive arena. In fact, there are battles taking place in many other foundry segments, such as 2.5D/3D packag... » read more

Manufacturing Bits: March 17


EUV source firm seeks help In 2012, a startup called Zplasma came out of stealth mode and introduced its first technology—a next-generation power source for extreme ultraviolet (EUV) lithography. But after much fanfare and hope, Zplasma has been unable to commercialize its EUV source technology. The company has also been unable to attract a development partner or outside funding. And t... » read more

Time To Look At SOI Again


Chipmakers have the luxury of looking at several process options when developing chips at the 28nm node and beyond. Using bulk CMOS, for example, chipmakers can scale planar transistors down to 20nm. Then, at 20nm, planar runs out of gas due to the so-called short-channel effect. At that point, IC makers must migrate towards finFETs at 16nm/14nm and beyond. Another process option is fully... » read more

Manufacturing Bits: Oct. 14


Toyota’s power steering IC Today’s cars are making use of more electronics. The increase in electronic content is driving the need for high temperature and high voltage chips. The electric power steering (EPS) system is one example. EPS provides power assist even when the engine is stopped. It also improves fuel economy compared to hydraulic power steering, according to automotive giant... » read more

Manufacturing Bits: Sept. 23


The annual IEEE International Electron Devices Meeting (IEDM) will take place in San Francisco from Dec. 15-17. As usual, there will be presentations on the latest technologies in a number of fields, such as semiconductors, bio‐sensors, energy harvesting, power devices, sensors, magnetics, spintronics, two-dimensional electronics, among others. Here’s just some of the papers that will be pr... » read more

Has The IC Industry Hit A ‘Red Brick Wall’?


In the mid-1980s, the semiconductor industry was in a crisis. Chipmakers were looking for ways to break the magical one-micron barrier. Many thought X-ray lithography would be required to break the barrier, but as it turned out, traditional optical technology did the trick. And the industry marched on. Then, in 2000 or so, the IC industry was nearing the so-called “red brick wall,” which... » read more

The Search For The Next Transistor


In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond. The industry has been exploring a number of next-generation transistor candidates, but suddenly, a few technologies are ... » read more

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