Demand for performance, power and area are creating increased design complexity, which subsequently can cause yield issues.
In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quantify and measure design changes and the degree of layout regularization. This new approach allows engineers to perform a full profiling across all patterns that exist in design and without needing to explicitly specify what patterns to analyze.
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