7/5nm Timing Closure Intensifies

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns

In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

Overcoming The Limits Of Scaling

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Power/Performance Bits: May 24

Reducing MRAM chip area Researchers from Tohoku University developed a technology to stack magnetic tunnel junctions (MTJ) directly on the via without causing deterioration to its electric/magnetic characteristics. The team focused on reducing the memory cell area of spin-transfer torque magnetic random access memory (STT-MRAM) in order to lower manufacturing costs, making them more compe... » read more

Tech Talk: Configurable Logic

Cliff Lloyd, business development director at NXP Semiconductors, talks about designing in one part for many functions to reduce power consumption and cost. [youtube vid=ut5kCm0kNwE] » read more

Reality Check: A Guide To Understanding Optimized Processor Cores

The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation ... » read more

Building An Efficient, Tightly-Coupled Embedded System Using An Extensible Processor

The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems. As a consequence, the power, performance and area (PPA) ratio of these systems also shifts in favor of performance at the cost of power and area... » read more

Tech Talk: Power, Performance And Area In 2.5D

The cost will be comparable at first, but the only way to improve power, performance AND area at the same time will be with a different architectural approach. [youtube vid=XAbE7jpjuMA] » read more

Guesswork, And Other Design Paradigms

PPA for soft IP seems like an oxymoron. How do you determine the implementation characteristics (PPA — Power, Performance and Area) for something that has not yet been implemented? Flying blind until implementation would be a rookie move. More likely you are going to estimate based on a prior implementation. Not a bad approach if the IP hasn’t changed significantly and the target library is... » read more

New Challenges, New Name

As you’ll notice today, we’ve changed our name from Low Power Engineering to Low-Power/High-Performance Engineering. We don’t take name changes lightly—we've been discussing this in depth with readers, sponsors, and researchers for the past six months. The almost universal conclusion is there is a big shift underway in the semiconductor industry today, and our new logo is a better refle... » read more