Using ASICs For AI Inferencing


Flex Logix’s Cheng Wang looks at why ASICs are the best way to improve performance and optimize power and area for inferencing, and how to add flexibility into those designs to deal with constantly changing algorithms and data sets. https://youtu.be/XMHr7sz9JWQ » read more

eFPGA vs. FPGA Design Methodologies


Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

Safety, The Non-Negotiable Requirement Driving Autonomous Vehicle SoC Designs


The automotive industry has set itself the goal of achieving autonomous driving and is accruing the building blocks to make that happen. The challenge is in architecting the next generation automotive SoCs which must deliver exploding performance while meeting requirements for real-time latency, end-to-end QoS, FuSa (ISO 26262) and security. These SoCs need to include heterogeneous architecture... » read more

22nm Process Technology


Jamie Shaeffer, senior director of product line management at GlobalFoundries, talks about how FD-SOI compares with bulk technologies, where it will be used and why, and future stacking options. https://youtu.be/2i7GJRxcNRs » read more

In-Design Power Rail Analysis


Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

7/5nm Timing Closure Intensifies


Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns


In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

Overcoming The Limits Of Scaling


Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Power/Performance Bits: May 24


Reducing MRAM chip area Researchers from Tohoku University developed a technology to stack magnetic tunnel junctions (MTJ) directly on the via without causing deterioration to its electric/magnetic characteristics. The team focused on reducing the memory cell area of spin-transfer torque magnetic random access memory (STT-MRAM) in order to lower manufacturing costs, making them more compe... » read more

Tech Talk: Configurable Logic


Cliff Lloyd, business development director at NXP Semiconductors, talks about designing in one part for many functions to reduce power consumption and cost. [youtube vid=ut5kCm0kNwE] » read more

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