Minimizing Power Consumption In Next-Generation Mobile Devices

What’s at issue, what techniques are being used to solve problems and what does the future hold.


By Cheryl Ajluni

Today’s consumers continually demand ever more efficient and reliable means of mobile communication. At the same time, the wireless industry is evolving toward higher data rates and capacities. Both of these trends present a wealth of opportunity for innovative system engineers looking to design the next generation of mobile communication devices. They also pose some interesting challenges, not the least of which is power.

Mobile devices are today like miniature computers and, as such, a great deal of power is required to support the range of features and applications they now offer. This requirement will only increase with future generations of mobile devices. But consumers are demanding longer battery life to ensure that their mobile devices stay powered for as long as possible. Unfortunately, there are only so many ways that these issues can be addressed, including utilization of new technologies and techniques for reducing power consumption and replacing the battery altogether, just to name a few. Let’s take a closer look at these options and what they may mean for the future generation of mobile communication devices.

Power Issues

Understanding power consumption is the first step in learning to minimize it in a mobile device. In a digital circuit, power consumption can be classified as either dynamic or static. Dynamic power is due to the capacitances inherent in CMOS circuits as they are switched between low and high voltage values. Static power consumption is due to leakage current in the circuit’s transistors and is mostly determined by the size and number of transistors on a device.

To ensure acceptable battery life, system designers must pay careful attention to the power consumption in their designs. Various power management strategies and power-optimization techniques, spanning all levels of design abstraction, can help the engineer achieve sufficiently low power consumption. Dynamic power consumption, for example, can be minimized at the layout or gate level by reducing wire capacitance and restructuring logic to minimize switching activity. Leakage power can also be minimized at the gate level using multi-threshold standard cells. By far though, the greatest reduction in power consumption, whether dynamic or static, comes from utilization of power-optimization techniques at the system level.

Exploring power-saving options

At the system level, static (e.g., leakage) and dynamic power both can be affected by employing a range of techniques. Which technique to use will often depend on the target application in question. Some of the basic techniques for minimizing power consumption include automatic clock gating and multi-threshold voltage libraries. More aggressive power savings come from advanced techniques like multiple supply voltage and power shutoff. A multiple supply voltage technique is useful in designs where everything is always running at full speed. In contrast, power shutoff is used in designs where large portions of the device are not always active, such as in a handset. Dynamic frequency involved scaling is another technique whereby the design is dynamically adjusted to meet only the requirements that exist at any given time. At the system level, where CPU and memory are dominant power-consuming subsystems, memory hierarchy and dynamic voltage and frequency scaling technique (DVFS) are considered the most optimal power-saving techniques. Other techniques to consider include:

  • Gating Techniques: Clock gating, whether combinational or sequential, is just one gating technique that can be used to minimize power consumption in a design. Power and data gating are two other alternatives. Power gating is similar to clock gating in that cells that do not perform a required computation are turned off using sleep transistors. Instead of disabling just the clock signal, sleep transistors also disconnect cells from their power supply. As a result, power gating reduces both dynamic and static power consumption. Data gating, is a technique whereby data inputs of functional units are gated depending on whether output values are used.

  • ESL Power Analysis: While employing specific power-saving techniques can be effective, another alternative utilizes specially designed EDA software at the Electronic System Level (ESL) to reduce power consumption. With this software, system engineers can anticipate the system’s power consumption early in the design flow and then quickly explore the impact of different design alternatives (e.g., different bus topologies or IP blocks) on that expected power consumption. The engineer also can make decisions regarding which power management strategies to implement and then verify whether or not these strategies will allow power targets to be met. Most of the major EDA vendors and a number of startups have developed low-power synthesis tools to analyze power consumption at the system level using activity data, which can save significantly more power than RTL done by hand. By letting system engineers synthesize power-efficient RTL architectures from the ESL, significant power optimization can be achieved.

  • Process Techniques: While traditional power management techniques like low-power modes, clock gating and DVFS will continue to be useful, new process techniques can also be used to solve low-power design challenges. One grouping of techniques comes from Texas Instruments and is available in the company’s second-generation SmartReflex power and performance management technologies. SmartReflex will be integrated into both custom and standard devices at the 90-, 65-, 45-nm process nodes and below. Comprised of intelligent and adaptive hardware and software techniques, SmartReflex 2 dynamically controls voltage, frequency and power based on device activity, modes of operation and temperature. These techniques feature a number of innovations such as adaptive voltage scaling, dynamic power switching and standby leakage management, and accomplish a variety of goals including reducing static leakage power at the silicon IP level; coordinating the power consumption and performance of all major system components, and enabling a granular approach to partitioning a device’s power domains.

A future without batteries

While power-saving techniques can be effective in minimizing power consumption in battery-operated mobile devices, what if there was a way to eliminate batteries altogether? The key to this vision lies in being able to transmit power to, for example, a laptop or cell phone, as easily as we now transmit information via wireless power technology.

Recently, Intel joined forces with physicists from Massachusetts Institute of Technology to explore the resonant induction phenomenon (e.g., using resonant magnetic fields to wirelessly transmit electricity) which makes wireless power safely possible. The result of that exploration, Intel’s Wireless Resonant Energy Link (WREL), was demonstrated at the Intel Developer Forum in August. During the demonstration, a WREL unit transferred 60 watts over two feet with 75 percent efficiency (Figure 3). While initially, WREL will be used to charge batteries in laptops, cameras and cell phones when they get within several feet of a transmit resonator, Intel hopes its technology will eventually eliminate the use of batteries altogether.


At the August, 2008 Intel Developer Forum, WREL was used to wireless power a 60-watt light bulb which consumes more power than an average laptop computer. The demonstration involved two metal arrays connected to a power amplifer. The arrays resonated at a certain frequency to establish an energy link, transmitting power from one array to the other.

Of course Intel is not the only company investigating ways to deliver wireless power to today’s increasingly wireless world. Fulton Innovation (, Powercast (, WildCharge (, and WiPower ( have already shown simpler versions of wireless power technology.


Due to high frequencies and submicron feature sizes, predicting and managing the power consumption in next-generation SoCs remains a major challenge. Power, therefore, will continue to be a driving requirement in mobile device development. While current techniques are focused on minimizing power consumption, wireless power may one day make those efforts somewhat irrelevant. In the meantime, as long as system engineers design innovative new communication features and applications, ways to efficiently and cost-effectively power them for longer and longer lengths of time will be one requirement that never goes away.