New Low-Power Memory Interface Ahead

By Pallab Chatterjee
The trend in consumer electronic devices is toward a multimedia-centric data flow, forcing changes in the memory interface needed to handle it.

The increased compute resources needed for video signal processing, along with high-definition audio, used to be the exclusive domain of mainstream desktop computers and servers due to their access to memory and high data throughput. The evolution of mobile processors since has pushed these tasks into battery-operated devices, which have a low dynamic operating requirement.

These devices, which include everything from tablet PCs to netbooks, smart phones, and handheld gaming systems, are becoming the platform of choice for playback of these multimedia data sets. Progress has been made in the power/performance envelope for the processors, and now SPMT (Serial Port Memory Technology) is bringing a comparable advance to memory architecture.

To address the needs of these mobile devices, the SPMT solution has embraced the shift from parallel to serial. As has happened with computer I/O ports (parallel I/O and serial 25 pin to USB), PCI to PCI Express, and parallel ATA to 1.5G, 3G and 6G SATA, device memory is also changing. The reduced pin count and the ability to build local high-speed SERDES up to 12.8GB/s is the mainstay of the SMPT technology. The serial memory solution uses a small voltage swing, so it features differential signaling for increased reliability. The challenge has been the incompatibility with legacy systems, which has slowed adoption because of increased risk.

To remedy that, the SMPT group has created and adopted a SerialSwitch technology to address the power penalty at low bandwidths over parallel interfaces and the legacy interface issue. SerialSwitch is a technology that operates in parallel mode, with the low power factor of LPDDR2 at low data rates, and then switches to the power performance characteristics of the serial interface. This eliminates the startup latency of the memory as well as the traditional PLL lock times when switching to active mode. The technology specifically works by multiplexing an eight-lane bi-directional serial interface and an x16 LPDDR2 parallel interface onto the same pads. The parallel interface also ensures backward compatibility with existing LPDDR2 connections and system designs, making the transition to the new memory format easier. (See figure 1.)

Fig. 1

SPMT is the first serial data specification that is targeted specifically for memory. Its initial version supports 6.4Gb/s bandwidth per chip using standard 400MHz clocks. The backward compatibility includes both pin assignments and signals, as well as the command bus & commands and the system timing. As the target market is the mobile application space, special attention was paid to making sure the memory has a very low latency exit from power-down states, and can integrate with existing memory cores in current revision designs.

The new memory format supports four times the bandwidth as LPDDR2 for a given pinout, and half the power for a given bandwidth. Consider, for example, LPDDR2 memory with 800Mbps data rate per lane, 400MHz interface logic, an x128 (4×32) memory width needs 56 address pins and 176 data pins to yield a total bandwidth of 12.8GB/s at 720 mW. By comparison, the SMPT memory yields an 8Gbps data rate per lane, the same 400MHz interface logic, 32 lanes of interface width (equiv to x64 LPDDR2), and only needs 28 address pins and 88 data pins for a total bandwidth of 25.6GB/s for the same 720mW.

The SPMT memory will fit in a manufacturing-proven PoP216 package. With any new interface format, especially those directed as power savings, the issues of manufacturability and test always come into play. SPMT is no exception. The specification calls for the chips to use the same die and package test as parallel memory, utilize BIST for the serial interface and result in the same testing time as standard LPDDR2 parallel memory.

The format is being backed by ARM, Hynix, LG, Marvell, Samsung and Silicon Image. It is expected to appear in products in the marketplace in near term.