Noise Issues At 10nm And Below

Most of the conversations below 10nm have been about lithography, materials and design constraints. But as companies push to 7nm and beyond, they are faced with a host of new challenges, including how to deal with electromagnetic crosstalk.

Electromagnetic crosstalk is unwanted interference caused by the electric and magnetic fields of one or more signals (aggressors) affecting another signal (victim). This phenomenon is also referred to as coupling or noise. While this isn’t a new challenge, at advanced nodes it has progressed from a pesky third- or second-order effect to a potentially expensive and time-consuming first-order problem.

Crosstalk occurs via two mechanisms. One is capacitive crosstalk, which is caused by the electrical field. The second, inductive crosstalk, is caused by the magnetic field. To help understand the complexities of EM crosstalk analysis, let us contrast that problem with that of analyzing capacitive coupling in digital designs using noise analysis tools. Capacitive coupling is stronger at close proximity and fades out at longer distances, so these tools can and do safely ignore coupling between signal lines that are not physically close to each other. In addition, these tools completely ignore inductive magnetic coupling.

The problem of analyzing EM crosstalk is more challenging. To begin with, the symptoms of the problem do not neatly package themselves into one metric like timing failure. Those often manifest themselves as the degradation of some key performance criterion that varies from design to design. Identifying the issue as being crosstalk-related is the first challenge. To make matters more complex, EM crosstalk usually involves unwanted coupling between digital and sensitive analog/RF blocks, with either one being the potential aggressor or victim. By its very definition, EM crosstalk needs to be identified, debugged and resolved differently in different designs. The existence of this problem is well established and the solution so far has been tricks in architecture in higher layers of hardware or software to prevent modes of operation that trigger the problem. However, this is becoming financially—and in some cases technically—untenable as the designs have grown in complexity and speed.

A major complexity associated with EM crosstalk is the staggeringly complex scope of physical structures that need to be handled in order to create a complete EM model of the signal nets of interest. Consider surrounding nets, for example, plus all the surrounding structures that can contribute to crosstalk. That includes power and ground routing layers, bulk silicon substrate, package layers, bond/bump pads with their routing layers, seal rings, metal fill, de-coupling caps, etc. Note that most of these structures have complex physical layouts and they need to be properly meshed to extract resistance, capacitance, inductance, coupling capacitance, and mutual inductance.

A second complexity factor can be illustrated by considering the following question: Given a potential victim signal, can we analyze EM crosstalk by limiting our focus to a small bounding box in the design? The answer, unfortunately, is no.

Analyzing the neighborhood of a victim signal works well for electrical capacitive coupling only. However, a magnetic field can travel along relatively large loops that are formed by structures outside the immediate neighborhood of a victim signal and can sometimes encircle the whole layout of the chip.

Finally, the output model generated by EM crosstalk tools can be extremely complex because it includes all the nets that contribute to the crosstalk problem plus all the nets and structures that might have an impact on the performance of the circuit.

However, the output model must also satisfy the following key criteria to be useful for further processing:

• Easy simulation with a SPICE-type simulator in a reasonable amount of time,
• Suitability for all kinds of non-linear and noise simulations with SPICE, and
• Easy back annotation in a rather complex and hierarchical design database that crosses the boundaries of blocks or silicon dies.