An alternative to the standard fault isolation techniques for both low-volume test vehicles and product ramp.
Yield ramp for ICs designed on advanced process technologies faces new challenges because of the very complicated silicon defect types and defect distribution. Yield ramp and yield improvement are not just about profitability and time-to-market, but also have a role in today’s electronics supply chain crisis. That means yield ramp affects not just the IC maker, but the global economy.
Every new manufacturing technology starts out with a low yield that improves over time (figure 1). In early node qualification, the scan chain fail rate on test chips is very high. At the same time, the volume of chips is low, which limits how much yield learning is accomplished. Once a company has moved on to testing product qualification vehicles instead of test chips, the chain and logic failure is about equal and there is more data to work with. Once companies get to the real product, they can do systematic yield learning to remove the systematic logic defects.
A common theme between all these stages of node qualification and product introduction is that the failure analysis tools are reaching their limits of resolution, so they have a very hard time finding defects. If you can’t find the defects, then you can’t find the root causes that allow you to improve yield.
The semiconductor industry needs alternatives to the standard fault isolation techniques and very high-resolution diagnosis results for both low-volume test vehicles and product ramp. This demand has led to a new diagnosis technology that takes advantage of reversible scan chain architectures to generate patterns that improve scan chain diagnosis resolution.
So why is chain diagnosis critical for yield ramp? In the initial ramp stage, chain failures can account for ~66% of chip failures (figure 2). If you can’t solve the chain issues quickly, you’ll have a hard time getting to high-yield product stage.
Fig. 2: Chain defect and yield.
Once defects are detected, they have to be “root caused”—there has to be an image of the defect showing the failure mechanism. To do that, the wafer must go through a number of processing steps for transmission electron microscopy (TEM) imaging. The toolset used to do this is complex and expensive. It can cost in the neighborhood of $20 million and require skilled engineers to find the defect. It can take days to make a good sample and there can be a failure analysis queue of weeks to months. If the defect isn’t found with very high resolution, all that time and money go to waste.
In traditional chain diagnosis, the patterns are loaded to the right and unloaded to the right. Figure 3 illustrates a very simple chain. Say a defect is detected in the 4th cell. As that data shifts out, there will ambiguity in defects that might exist in cells 5 and 6. This introduced too many suspects, which means low diagnosis resolution and more difficult failure analysis.
Fig. 3: Standard chain diagnosis.
So what if we could shift in one way, and shift out the other way? This presents a solution to the resolution problem. Load to the right and unload to the left, as shown in figure 4, find the leftmost defect location. This reduces the number of suspects, making it easier to isolate the defect. You then use the same pattern data loaded to the left and unloaded to the right to diagnosis the rightmost defect location. In this simple example, the unloaded data shows the same difference in both directions, indicating the exact defect location.
Fig. 4: Reversible chain diagnosis.
This technology is called reversible chain diagnosis, and it is proven in silicon to show the following benefits:
The success of this approach marks a significant advancement in diagnosis. It fits into existing flows with small changes and needs only chain test patterns for diagnosis. Reversible chain diagnosis can aid in the race to entitlement yield, especially at leading technology nodes.
For more details, read the white paper Reversible Chain Diagnosis.
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