1-on-1 With Intel’s Foundry Chief

By Mark LaPedus & Ed Sperling
Semiconductor Engineering sat down to discuss foundry trends, IC scaling, chip-packaging and other topics with Sunit Rikhi, vice president of the Technology and Manufacturing Group at Intel and general manager of Intel’s Custom Foundry unit.

SE: Where is Intel at in the foundry business today?

Rikhi: We started with a very narrow set of customers. Now, we are definitely past the initial stages. We are building up our capabilities to offer our services for a wider range of customers. We now have silicon flowing through the fab. We have design starts at the front end of the pipeline. So now, we have four years’ worth of activities and experience going from the beginning of the pipeline to the end of the pipeline. Now, our ability to offer technology for new customers is expanding. So, we are in the second stage of our growth in the foundry business.

SE: Intel recently added a new foundry customer in Panasonic. The company also has expanded its 14nm technology offerings with a low power foundry process. What’s going on there?

Rikhi: We have offered 22nm technology. In 14nm, we have expanded our process portfolio to cover both LP (low power) and GP (general purpose). For GP and LP, we are talking to many customers. Panasonic was one of the LP customers. Panasonic, as I understand it, did not make the switch from an IDM to a fabless company on this deal with us. They have an existing relationship with a foundry. They are coming from that relationship and selecting a 14nm process over a 16nm process. They selected us. So that’s a new customer.

SE: How far is Intel going into the advanced 2.5D/3D stacked die and the system-in-packaging markets?

Rikhi: Quite a bit. We don’t use the term 2.5D internally. We use SiP technology. These are high-bandwidth connections between chips for performance. There is also research going on all the way up to 3D. But at this stage, I am not at liberty to disclose what we are doing in 3D. We have customers. Altera, for instance, has announced with us a form of multi-die packaging technology.

SE: How would you describe that multi-die packaging technology?

Rikhi: It’s heterogeneous.

SE: Are the EDA tools there to make 2.5D/3D stacked die happen?

Rikhi: I believe so, although it is far from production. It’s all under development. And so as the technology is developed, and intersected with actual product, we may discover the need for more and improved tools. But so far, the tools are not a limitation.

SE: When will 2.5D/3D chips become a mainstream technology?

Rikhi: It’s still unclear when we will see the mainstream in terms of volumes. But the time has come for us to apply multi-die heterogeneous and system-in-package as part of our offerings.

SE: On your roadmap, Intel thinks it can scale to 3nm and beyond, right?

Rikhi: That’s still in research.

SE: When do you begin to see the tradeoffs in traditional scaling versus moving more aggressively in advanced die stacking?

Rikhi: Now is not the time to blink. This is not the time to say let’s go up or stack instead of doing traditional scaling. Going up or stacking is an independent path from traditional scaling. You don’t have to make a choice between exploiting packaging technology and Moore’s Law.

SE: Does the platform for logic become more narrowly defined as you continue to scale?

Rikhi: On the contrary, we have an SoC offering in 14nm and 10nm. We also intend it for 7nm as well. We want to integrate just about everything. Obviously, the more you integrate on a chip, there are fringe elements that appear. They may not belong on the chip.

SE: Is that the analog portions of the SoC?

Rikhi: I remember having this discussion at 32nm. By the time 14nm appears, the people thought that the analog stuff will be off chip. But today, we have SerDes technology on 14nm. How did we make that possible? We have a highly digital architecture, which mixes digital and analog. We get that in the smallest die possible with good performance and power.

SE: How would you compare yourself to TSMC now?

Rikhi: They have the experience and wisdom of being in the industry for 30 years as a full service foundry. But our heart is in the right place. Customers are teaching us. And the ecosystem partners are teaching us. So we are learning very fast, but we don’t pretend to know how to spin services as well as they do. But on the technology side, there is no question. We have the best technology. For example, before and at 22nm, we had the best transistors, but not the best interconnects. We’ve changed that. At 14nm, we have an entire generation of new technology. So for power and performance, and the economic benefit of Moore’s Law, we are the ones to beat.

SE: Has it been more difficult to obtain foundry customers than previously thought?

Rikhi: Absolutely. There are people who thought all Intel had to do was to enter the business. And then, customers would come. In fact, there were those who thought people would beat our doors down and break them. And then, there were people who thought there was no way Intel is going to succeed in the foundry business, because of a number of concerns. For example, how can you trust Intel to obtain capacity and all of that kind of stuff? So you have both ends of the spectrum, but as it turns out, none of them are true. It’s somewhere in the middle. I get to talk to everybody because of the technology that is in our pocket, but I don’t get to walk away with contracts. It is far more than the technology we have to sell for the customers to actually make a switch. And that’s something a lot of people don’t appreciate and understand.

SE: Where is Intel seeing success in the foundry business?

Rikhi: The infrastructure and telecom segments. The hunger for technology is huge. Speed and power are key. Our successes include companies in the FPGA area. There are other customers who have not announced foundry agreements with us as well.

SE: Are you shipping 14nm chips yet?

Rikhi: We are shipping silicon. It’s prototype silicon.