Optimizing Analog With Layout In The Loop

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly optimized schematic often achieves significantly degraded performance. To mitigate this effect, experienced design engineers often anticipate layout-induced parasitics by integrating typical parasitic values manually into the schematic. While this reduces the degradation, performance remains far from perfect. Especially in more advanced nodes, parasitics become much more severe and less predictable.

As a result, methodology and automation – whether integrated into the design environment or provided by add-on tools – become crucial for improving estimation or even enabling (partial) layout extraction as early as possible in the design process. This reduces the time to layout, while the shorter cycle time enables more iteration runs with more accurate parasitic values. Consequently, the optimization focus shifts from pure schematic to layout-aware. At first glance, the results may appear worse, but in reality, they provide a much more precise understanding of the problem. This, in turn, enables optimization that leads to better sizing and reduces sensitivity to parasitic effects, as these are already considered to some extent in the optimization process.

The implementation of such optimization can be broadly divided into three levels. First, a coarse parasitic estimation can be defined based on, e.g., a few custom-placed critical parasitics. Their values should be derived using a formula that combines sheet resistances and capacitances with key layout parameters (such as device sizes plus the resulting array size) to incorporate major layout influences into the optimization. Second, building blocks (such as current mirrors) can be automated by tools within the design environment or by third-party tools. Here, partial layout extraction is enabled early, which – combined with the sizing of the schematic – leads to better parasitic estimation, albeit at the cost of somewhat longer optimization cycles. Third – and probably more of a paradigm-shifting approach – is the automation of an entire (and well-selected) design building block as some sort of “Soft IP.” This automates candidate generation for both the schematic and the layout, meaning it can be combined with parasitic extraction and optimization via scripts to ultimately automate the entire loop.

From the first to the last method, the simulation time increases, but so too does the accuracy and the level of automation. That means it is up to the designer, the design team, or even the company’s business case to determine which approach to use at each project phase. This is a challenging and fascinating endeavor, and there are ways to incorporate more methodology to improve design performance at lower power while accelerating design time. In the long run, the focus should shift from designing specific IP toward establishing processes that can handle larger portions of the iterative work inherent in every new IP development.

More information about automated analog design methodology can be found here: https://www.eas.iis.fraunhofer.de/en/business_areas/efficient_electronics/automated-analog-design.html