Options And Hurdles Come Into Focus For 3D Stacking

By Mark LaPedus
The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market.

There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs.

The enormous risk to bring these chips to market means that vendors must develop a sound and cost-effective strategy on all fronts. In one part of the wafer-level packaging flow, for example, chipmakers must choose between one of the three main vertical stacking techniques: die-to-die, die-to-wafer and wafer-to-wafer.

Each stacking technique has its advantages and disadvantages. The decision to go with one technique or another depends on the product type, process flow, and, of course, cost. And it also involves some changes in the interconnect material and wafer bonding methodology.

The early stacking trends are becoming apparent: The 2.5D/3D chip market is currently embracing die-to-die (sometimes called chip-to-chip), with die-to-wafer in the works. Wafer-to-wafer has moved into applications such as image sensors, but the technology is still in the distant future for chip production.

“I think the biggest challenge for the whole process is yields,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

“Die-to-die is the first implementation. In die-to-die, you can manage the warpage and isolate the yield,” McCann said. “Wafer-to-wafer will take place in the future, but you bring yield issues into your business model.”

Another foundry, Taiwan Semiconductor Manufacturing Co. (TSMC), recently rolled out its Chip-on-Wafer-on-Substrate (CoWoS) offering. This is a turnkey line that includes both the front- and back-end steps for 2.5D/3D production. Technically, CoWoS is a die-to-die scheme, but it could also be classified as die-to-interposer.

Bottleneck in 3D flow
In the overall 2.5D/3D manufacturing flow, there are a number of process steps. There are five main front-end TSV or via creation process steps: etch, chemical-vapor deposition, physical-vapor deposition, electroplating, and chemical mechanical polishing.

The bigger manufacturing bottlenecks reside at the back-end. In this flow, a processed wafer with TSVs goes through the following steps: wafer bumping, thinning, stacking and bonding. Test is conducted at the wafer level and during various points in the flow.

Test and the temporary bonding/debonding steps are still the big challenges. Though not as daunting, there are some challenges in the various stacking techniques, including die-to-die.

One of the first 2.5D chips in the market is Xilinx’s Virtex-7 2000T FPGA. The recently announced 2000T is a 28nm part, in which four FPGA slices are stacked on a 65nm interposer. Technically, Xilinx’ FPGA utilizes chip-to-chip and die-to-interposer stacking.

Emerging 3D memory devices utilizing Wide I/O also will implement die-to-die. Related to stacking, the industry is also moving to an emerging interconnect scheme called fine-pitch copper pillar bumps for 2.5D/3D designs.

For years, many 2D designs have used conventional flip-chip solder bumps. More recently, copper pillar bumps have been implemented in various 2D designs, when there is a need for low-profile and high-connectivity applications.

“Copper pillar gives you a tighter pitch,” said Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials. Flip-chip solder bumps enable 40-u pitches, compared to 20-u for copper pillar, Ramaswami said.

The transition to copper pillar bumping appears to be rather painless, but there are some issues in the vertical stacking flow. Compared to the other stacking techniques, die-to-die is well understood, and the supply chain is relatively straightforward.

The die-to-die equation becomes more difficult in heterogeneous designs, where the individual parts may come from two or more vendors. This complicates the stacking flow and brings yield into the equation. “That’s where the (importance of a good) supply chain comes in,” Ramaswami said.

The other problem with die-to-die is throughput and cost. In die-to-die, the components are assembled and aligned with traditional pick-and-place tools. The throughputs are slow, sometimes averaging 360 dies an hour. “The problem is more pronounced if the dies are small,” said Thorsten Matthias, head of business development at EV Group, a supplier of semiconductor equipment.

Regarding the assembly flow, Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE), added: “It’s really a challenge to handle these thin wafers. Warpage is a big challenge.”

3D devices will require ultra-thin wafers of 100 µm and below, but these substrates are less stable and prone to stress in the flow. This will require a manufacturing step called temporary bonding and debonding, which is still a relatively slow and expensive process.

For this and other reasons, the 2.5D/3D devices themselves are expected to remain expensive. “But for very large die, you can still achieve a cost reduction,” Rice said.

Other stacking options
There are even more challenges in die-to-wafer, which appears to be in R&D or the pilot line stage. Die-to-wafer also has many of the same inherit problems as die-to-die. There are supply chain issues. Both flows will implement expensive temporary bonding/debonding steps.

“The question is how you are going to test it? You really need known-good die (KGD) to put these things together. You also need to make sure your interposer is good,” Rice said.

Still, many chip makers have put die-to-wafer on their roadmaps to lower their costs and boost their throughputs, EV Group’s Matthias said. The other advantage is that “you can control or eliminate warpage,” he said.

Meanwhile, for decades, the industry has been talking about wafer-to-wafer stacking. Wafer-to-wafer enables the highest throughput, but it requires that the dies have the exact same size when bonding. But if a defective die is bonded to a good die, it destroys the whole stack. “Wafer-to-wafer is a long ways off,” said E. Jan Vardaman, president of TechSearch International Inc., a research firm.

To accelerate wafer-to-wafer, the industry is exploring new bonding technologies. Today’s 2.5D/3D devices, based on TSVs and copper pillars, are implementing metal-to-metal thermocompression bonding. This methodology has the advantage of forming the mechanical and electrical bonds in one step.

The industry is also looking at copper-to-copper thermocompression bonding. “Copper-to-copper is a must if you are targeting the highest possible electrical performance at less than 10-u,” EV Group’s Matthias said. But this technology is a slower process and not expected to move into volume production for another two to three years.

Another technology, fusion wafer bonding, could one day enable wafer-to-wafer for 3D chip integration. Fusion bonding is a two-step process consisting of a room temperature bonding step and an annealing step at elevated temperature. EV Group and others sell fusion bonders.

Using one form of fusion bonding technology, dubbed direct oxide bonding, Ziptronix Inc. has demonstrated the ability to reduce distortion in backside illuminated (BSI) image sensors. Ziptronix’ ZiBond process can be performed as wafer-to-wafer or die-to-wafer. The process initiates at room temperature without external force required.

The rival bonding solutions “are limited in terms of stress, cost and scalability,” said Paul Enquist, CTO and vice president of R&D at Ziptronix.

Ziptronix’ technology is in production for BSI image sensors. It’s unclear when chipmakers will adopt fusion bonding for wafer-to-wafer 3D integration. The adoption of new technology takes time. “Our technology has been ready for awhile,” he said. “Finally, the market is ready for the technology.”